Spartan-3E FPGA Family: Functional Description
Table 14: Carry Logic Functions (Cont’d)
Function
Description
CY0G
Carry generation for top half of slice. Fixed selection of:
·
·
·
·
G1 or G2 inputs to the LUT (both equal 1 when a carry is to be generated)
GAND gate for multiplication
BY input for carry initialization
Fixed 1 or 0 input for use as a simple Boolean function
CYMUXF
CYMUXG
CYSELF
CYSELG
XORF
Carry generation or propagation mux for bottom half of slice. Dynamic selection via CYSELF of:
·
·
CYINIT carry propagation (CYSELF = 1)
CY0F carry generation (CYSELF = 0)
Carry generation or propagation mux for top half of slice. Dynamic selection via CYSELF of:
·
·
CYMUXF carry propagation (CYSELG = 1)
CY0G carry generation (CYSELG = 0)
Carry generation or propagation select for bottom half of slice. Fixed selection of:
·
·
F-LUT output (typically XOR result)
Fixed 1 to always propagate
Carry generation or propagation select for top half of slice. Fixed selection of:
·
·
G-LUT output (typically XOR result)
Fixed 1 to always propagate
Sum generation for bottom half of slice. Inputs from:
·
·
F-LUT
CYINIT carry signal from previous stage
Result is sent to either the combinatorial or registered output for the top of the slice.
XORG
FAND
GAND
Sum generation for top half of slice. Inputs from:
·
·
G-LUT
CYMUXF carry signal from previous stage
Result is sent to either the combinatorial or registered output for the top of the slice.
Multiplier partial product for bottom half of slice. Inputs:
·
·
F-LUT F1 input
F-LUT F2 input
Result is sent through CY0F to become the carry generate signal into CYMUXF
Multiplier partial product for top half of slice. Inputs:
·
·
G-LUT G1 input
G-LUT G2 input
Result is sent through CY0G to become the carry generate signal into CYMUXG
X-Ref Target - Figure 23
The basic usage of the carry logic is to generate a half-sum
in the LUT via an XOR function, which generates or
propagates a carry out COUT via the carry mux CYMUXF
(or CYMUXG), and then complete the sum with the
dedicated XORF (or XORG) gate and the carry input CIN.
This structure allows two bits of an arithmetic function in
each slice. The CYMUXF (or CYMUXG) can be instantiated
using the MUXCY element, and the XORF (or XORG) can
be instantiated using the XORCY element.
LUT
COUT
B
A
MUXCY
Sum
XORCY
CIN
DS312-2_37_021305
Figure 23: Using the MUXCY and XORCY in the Carry
The FAND (or GAND) gate is used for partial product
multiplication and can be instantiated using the MULT_AND
component. Partial products are generated by two-input
AND gates and then added. The carry logic is efficient for
the adder, but one of the inputs must be outside the LUT as
shown in Figure 23.
Logic
The FAND (or GAND) gate is used to duplicate one of the
partial products, while the LUT generates both partial
products and the XOR function, as shown in Figure 24.
DS312 (v4.2) December 14, 2018
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