Spartan-3E FPGA Family: Functional Description
and write operations. There are four basic data paths, as
shown in Figure 30:
Block RAM
For additional information, refer to the “Using Block RAM”
chapter in UG331.
1. Write to and read from Port A
2. Write to and read from Port B
3. Data transfer from Port A to Port B
4. Data transfer from Port B to Port A
Spartan-3E devices incorporate 4 to 36 dedicated block
RAMs, which are organized as dual-port configurable
18 Kbit blocks. Functionally, the block RAM is identical to
the Spartan-3 architecture block RAM. Block RAM
synchronously stores large amounts of data while
distributed RAM, previously described, is better suited for
buffering small amounts of data anywhere along signal
paths. This section describes basic block RAM functions.
X-Ref Target - Figure 30
3
Write
Read
Write
4
Read
Spartan-3E
Dual-Port
Block RAM
Each block RAM is configurable by setting the content’s
initial values, default signal value of the output registers,
port aspect ratios, and write modes. Block RAM can be
used in single-port or dual-port modes.
Write
Write
2
1
Read
Read
Arrangement of RAM Blocks on Die
DS312-2_01_020705
The block RAMs are located together with the multipliers on
the die in one or two columns depending on the size of the
device. The XC3S100E has one column of block RAM. The
Spartan-3E devices ranging from the XC3S250E to
XC3S1600E have two columns of block RAM. Table 21
shows the number of RAM blocks, the data storage
capacity, and the number of columns for each device.
Row(s) of CLBs are located above and below each block
RAM column.
Figure 30: Block RAM Data Paths
Number of Ports
A choice among primitives determines whether the block
RAM functions as dual- or single-port memory. A name of
the form RAMB16_S[w ]_S[w ] calls out the dual-port
A
B
primitive, where the integers w and w specify the total
A
B
data path width at ports A and B, respectively. Thus, a
RAMB16_S9_S18 is a dual-port RAM with a 9-bit Port A
and an 18-bit Port B. A name of the form RAMB16_S[w]
identifies the single-port primitive, where the integer w
specifies the total data path width of the lone port A. A
RAMB16_S18 is a single-port RAM with an 18-bit port.
Table 21: Number of RAM Blocks by Device
Total
Total
Addressable
Locations
(bits)
Number of
Columns
Device
Number of
RAM Blocks
XC3S100E
XC3S250E
XC3S500E
XC3S1200E
XC3S1600E
4
73,728
221,184
368,640
516,096
663,552
1
2
2
2
2
Port Aspect Ratios
12
20
28
36
Each port of the block RAM can be configured
independently to select a number of different possible
widths for the data input (DI) and data output (DO) signals
as shown in Table 22.
Immediately adjacent to each block RAM is an embedded
18x18 hardware multiplier. The upper 16 bits of the block
RAM's Port A Data input bus are shared with the upper 16
bits of the A multiplicand input bus of the multiplier. Similarly,
the upper 16 bits of Port B's data input bus are shared with
the B multiplicand input bus of the multiplier.
The Internal Structure of the Block RAM
The block RAM has a dual port structure. The two identical
data ports called A and B permit independent access to the
common block RAM, which has a maximum capacity of
18,432 bits, or 16,384 bits with no parity bits (see parity bits
description in Table 22). Each port has its own dedicated
set of data, control, and clock lines for synchronous read
DS312 (v4.2) December 14, 2018
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Product Specification
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