Spartan-3E FPGA Family: Functional Description
The carry chain enters the slice as CIN and exits as COUT,
controlled by several multiplexers. The carry chain connects
directly from one CLB to the CLB above. The carry chain
can be initialized at any point from the BX (or BY) inputs.
Carry and Arithmetic Logic
For additional information, refer to the “Using Carry and
Arithmetic Logic” chapter in UG331.
The carry chain, together with various dedicated arithmetic
logic gates, support fast and efficient implementations of
math operations. The carry logic is automatically used for
most arithmetic functions in a design. The gates and
multiplexers of the carry and arithmetic logic can also be
used for general-purpose logic, including simple wide
Boolean functions.
The dedicated arithmetic logic includes the exclusive-OR
gates XORF and XORG (upper and lower portions of the
slice, respectively) as well as the AND gates GAND and
FAND (upper and lower portions, respectively). These gates
work in conjunction with the LUTs to implement efficient
arithmetic functions, including counters and multipliers,
typically at two bits per slice. See Figure 22 and Table 14.
X-Ref Target - Figure 22
COUT
YB
1
CYMUXG
Y
G[4:1]
A[4:1]
G-LUT
CYSELG
CY0G
G1 G2
YQ
D
FFY
XORG
GAND
1
0
BY
XB
1
4
CYMUXF
X
F[4:1]
A[4:1]
F-LUT
CYSELF
CY0F
F1
F2
XQ
D
FFX
XORF
CYINIT
FAND
1
0
BX
DS312-2_14_021305
CIN
Figure 22: Carry Logic
Table 14: Carry Logic Functions
Function
Description
CYINIT
Initializes carry chain for a slice. Fixed selection of:
·
·
CIN carry input from the slice below
BX input
CY0F
Carry generation for bottom half of slice. Fixed selection of:
·
·
·
·
F1 or F2 inputs to the LUT (both equal 1 when a carry is to be generated)
FAND gate for multiplication
BX input for carry initialization
Fixed 1 or 0 input for use as a simple Boolean function
DS312 (v4.2) December 14, 2018
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Product Specification
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