Spartan-3E FPGA Family: DC and Switching Characteristics
Speed Grade
Table 93: Timing for the IOB Three-State Path
Symbol
Description
Conditions
Device
-5
-4
Units
Max
Max
Synchronous Output Enable/Disable Times
TIOCKHZ Time from the active transition at the OTCLK input LVCMOS25, 12 mA
All
All
1.49
2.70
1.71
3.10
ns
ns
of the Three-state Flip-Flop (TFF) to when the
Output pin enters the high-impedance state
output drive, Fast
slew rate
(2)
TIOCKON
Time from the active transition at TFF’s OTCLK
input to when the Output pin drives valid data
Asynchronous Output Enable/Disable Times
TGTS
Time from asserting the Global Three State (GTS) LVCMOS25, 12 mA
input on the STARTUP_SPARTAN3E primitive to output drive, Fast
All
8.52
9.79
ns
when the Output pin enters the high-impedance
state
slew rate
Set/Reset Times
TIOSRHZ
Time from asserting TFF’s SR input to when the
Output pin enters a high-impedance state
LVCMOS25, 12 mA
output drive, Fast
slew rate
All
All
2.11
3.32
2.43
3.82
ns
ns
(2)
TIOSRON
Time from asserting TFF’s SR input at TFF to when
the Output pin drives valid data
Notes:
1. The numbers in this table are tested using the methodology presented in Table 95 and are based on the operating conditions set forth in
Table 77 and Table 80.
2. This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data
Output. When this is true, add the appropriate Output adjustment from Table 94.
3. For minimum delays use the values reported by the Timing Analyzer.
DS312 (v4.2) December 14, 2018
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Product Specification
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