Spartan-3E FPGA Family: DC and Switching Characteristics
Table 88: Setup and Hold Times for the IOB Input Path
Speed Grade
IFD_
Symbol
Description
Conditions
DELAY_
VALUE=
Device
-5
-4
Units
Min
Min
Setup Times
TIOPICK
Time from the setup of data at
the Input pin to the active
LVCMOS25(2)
IFD_DELAY_VALUE = 0
,
0
All
1.84
2.12
ns
transition at the ICLK input of the
Input Flip-Flop (IFF). No Input
Delay is programmed.
TIOPICKD
Time from the setup of data at
the Input pin to the active
transition at the IFF’s ICLK input. default software setting
The Input Delay is programmed.
LVCMOS25(2)
IFD_DELAY_VALUE =
,
2
3
XC3S100E
All Others
6.12
6.76
7.01
7.72
ns
Hold Times
TIOICKP
Time from the active transition at LVCMOS25(3)
the IFF’s ICLK input to the point IFD_DELAY_VALUE = 0
where data must be held at the
Input pin. No Input Delay is
,
0
All
–0.76
–0.76
ns
ns
programmed.
TIOICKPD
Time from the active transition at LVCMOS25(3)
the IFF’s ICLK input to the point IFD_DELAY_VALUE =
,
2
3
XC3S100E
All Others
–3.93
–3.50
–3.93
–3.50
where data must be held at the
Input pin. The Input Delay is
programmed.
default software setting
Set/Reset Pulse Width
TRPW_IOB Minimum pulse width to SR
control input on IOB
All
1.57
1.80
ns
Notes:
1. The numbers in this table are tested using the methodology presented in Table 95 and are based on the operating conditions set forth in
Table 77 and Table 80.
2. This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, add the
appropriate Input adjustment from Table 91.
3. These hold times require adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, subtract
the appropriate Input adjustment from Table 91. When the hold time is negative, it is possible to change the data before the clock’s active
edge.
Table 89: Sample Window (Source Synchronous)
Symbol
Description
Max
Units
TSAMP
Setup and hold capture window of an The input capture sample window value is highly specific to a particular
ps
IOB input flip-flop
application, device, package, I/O standard, I/O placement, DCM usage,
and clock buffer. Please consult the appropriate Xilinx application note
for application-specific values.
•
XAPP485: 1:7 Deserialization in Spartan-3E FPGAs at Speeds Up to
666 Mbps
DS312 (v4.2) December 14, 2018
www.xilinx.com
Product Specification
127
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