欢迎访问ic37.com |
会员登录 免费注册
发布采购

XC3S100E-4VQG100CS1 参数 Datasheet PDF下载

XC3S100E-4VQG100CS1图片预览
型号: XC3S100E-4VQG100CS1
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 572MHz, 2160-Cell, CMOS, PQFP100,]
分类和应用: 时钟可编程逻辑
文件页数/大小: 227 页 / 6528 K
品牌: XILINX [ XILINX, INC ]
 浏览型号XC3S100E-4VQG100CS1的Datasheet PDF文件第108页浏览型号XC3S100E-4VQG100CS1的Datasheet PDF文件第109页浏览型号XC3S100E-4VQG100CS1的Datasheet PDF文件第110页浏览型号XC3S100E-4VQG100CS1的Datasheet PDF文件第111页浏览型号XC3S100E-4VQG100CS1的Datasheet PDF文件第113页浏览型号XC3S100E-4VQG100CS1的Datasheet PDF文件第114页浏览型号XC3S100E-4VQG100CS1的Datasheet PDF文件第115页浏览型号XC3S100E-4VQG100CS1的Datasheet PDF文件第116页  
Spartan-3E FPGA Family: Functional Description  
Production Stepping  
The Spartan-3E FPGA family uses production stepping to  
indicate improved capabilities or enhanced features.  
Designs operating on the Stepping 0 devices perform  
similarly on a Stepping 1 device.  
Stepping 1 is, by definition, a functional superset of  
Stepping 0. Furthermore, configuration bitstreams  
generated for Stepping 0 are compatible with Stepping 1.  
Differences Between Steppings  
Table 71 summarizes the feature and performance  
differences between Stepping 0 devices and Stepping 1  
devices.  
Table 71: Differences between Spartan-3E Production Stepping Levels  
Stepping 0  
Stepping 1  
Production status  
Production starting  
March 2006  
Production from 2005 to 2007  
Speed grade and operating conditions  
JTAG ID code  
-4C only  
-4C, -4I, -5C  
Different revision fields. See Table 67.  
DCM DLL maximum input frequency  
90 MHz  
(200 MHz for XC3S1200E)  
240 MHz (-4 speed grade)  
275 MHz (-5 speed grade)  
DCM DFS output frequency range(s)  
Split ranges at 5 – 90 MHz and  
220 – 307 MHz  
(single range 5 – 307 MHz for XC3S1200E)  
Continuous range:  
5 – 311 MHz (-4)  
5 – 333 MHz (-5)  
Supports multi-FPGA daisy-chain configurations from  
SPI Flash  
No, single FPGA only  
No(1)  
Yes  
JTAG configuration supported when FPGA in BPI  
mode with a valid image in the attached parallel NOR  
Flash PROM  
Yes  
JTAG EXTEST, INTEST, SAMPLE support  
Yes: XC3S100E, XC3S250E, XC3S500E  
No(2): XC3S1200E, XC3S1600E  
Yes  
All Devices  
Power sequencing when using HSWAP Pull-Up  
PCI compliance  
Requires VCCINT before VCCAUX  
No  
Any sequence  
Yes  
Notes:  
1. Workarounds exist. See Stepping 0 Limitations when Reprogramming via JTAG if FPGA Set for BPI Configuration.  
2. JTAG BYPASS and JTAG configuration are supported.  
Ordering a Later Stepping  
Software Version Requirements  
-5C and -4I devices, and -4C devices (with date codes 0901  
(2009) and later) always support the Stepping 1 feature set  
independent of the stepping code. Optionally, to order only  
Stepping 1 for the -4C devices, append an “S1” suffix to the  
standard ordering code, where ‘1’ is the stepping number,  
as indicated in Table 72.  
Production Spartan-3E applications must be processed  
using the Xilinx ISE 8.1i, Service Pack 3 or later  
development software, using the v1.21 or later speed files.  
The ISE 8.1i software implements critical bitstream  
generator updates.  
For additional information on Spartan-3E development  
software and known issues, see the following Answer  
Record:  
Table 72: Spartan-3E Optional Stepping Ordering  
Stepping  
Number  
Suffix Code  
Status  
Xilinx Answer #22253  
http://www.xilinx.com/support/answers/22253.htm  
0
1
None  
S1  
Production  
Production  
DS312 (v4.2) December 14, 2018  
www.xilinx.com  
Product Specification  
112  
 复制成功!