Spartan-3E FPGA Family: Functional Description
do not require Power-On Surge (POS) current to
successfully configure.
Voltage Regulators
Various power supply manufacturers offer complete power
solutions for Xilinx FPGAs including some with integrated
three-rail regulators specifically designed for Spartan-3 and
Spartan-3E FPGAs. The Xilinx Power Corner website
provides links to vendor solution guides and Xilinx power
estimation and analysis tools.
Surplus ICCINT if VCCINT Applied before VCCAUX
If the V
supply is applied before the V
supply,
CCINT
CCAUX
the FPGA might draw a surplus I
current in addition to
CCINT
the I
quiescent current levels specified in Table 79,
CCINT
page 119. The momentary additional I
surplus current
CCINT
might be a few hundred milliamperes under nominal
conditions, significantly less than the instantaneous current
consumed by the bypass capacitors at power-on. However,
the surplus current immediately disappears when the
Power Distribution System (PDS) Design
and Decoupling/Bypass Capacitors
Good power distribution system (PDS) design is important
for all FPGA designs, but especially so for high performance
applications, greater than 100 MHz. Proper design results
in better overall performance, lower clock and DCM jitter,
and a generally more robust system. Before designing the
printed circuit board (PCB) for the FPGA design, please
review XAPP623: Power Distribution System (PDS) Design:
Using Bypass/Decoupling Capacitors.
V
supply is applied, and, in response, the FPGA’s
CCAUX
I
quiescent current demand drops to the levels
CCINT
specified in Table 79. The FPGA does not use or require the
surplus current to successfully power-on and configure. If
applying V
before V
, ensure that the regulator
CCINT
CCAUX
does not have a foldback feature that could inadvertently
shut down in the presence of the surplus current.
Configuration Data Retention, Brown-Out
Power-On Behavior
The FPGA’s configuration data is stored in robust CMOS
configuration latches. The data in these latches is retained
even when the voltages drop to the minimum levels
necessary to preserve RAM contents, as specified in
Table 76.
For additional power-on behavior information, including I/O
behavior before and during configuration, refer to the
“Sequence of Events” chapter in UG332.
Spartan-3E FPGAs have a built-in Power-On Reset (POR)
circuit that monitors the three power rails required to
successfully configure the FPGA. At power-up, the POR
If, after configuration, the V
or V
supply drops
CCINT
CCAUX
below its data retention voltage, the current device
configuration must be cleared using one of the following
methods:
circuit holds the FPGA in a reset state until the V
,
CCINT
V
, and V
Bank 2 supplies reach their respective
CCAUX
CCO
input threshold levels (see Table 74 in Module 3). After all
three supplies reach their respective thresholds, the POR
reset is released and the FPGA begins its configuration
process.
•
Force the V
or V
supply voltage below the
CCAUX
CCINT
minimum Power On Reset (POR) voltage threshold
(Table 74).
•
Assert PROG_B Low.
Supply Sequencing
The POR circuit does not monitor the VCCO_2 supply after
configuration. Consequently, dropping the VCCO_2 voltage
does not reset the device by triggering a Power-On Reset
(POR) event.
Because the three FPGA supply inputs must be valid to
release the POR reset and can be supplied in any order,
there are no FPGA-specific voltage sequencing
requirements. Applying the FPGA’s V
supply before
CCAUX
the V
supply uses the least I
current.
CCINT
CCINT
No Internal Charge Pumps or Free-Running
Oscillators
Although the FPGA has no specific voltage sequence
requirements, be sure to consider any potential sequencing
requirement of the configuration device attached to the
FPGA, such as an SPI serial Flash PROM, a parallel NOR
Flash PROM, or a microcontroller. For example, Flash
PROMs have a minimum time requirement before the
PROM can be selected and this must be considered if the
3.3V supply is the last in the sequence. See Power-On
Precautions if 3.3V Supply is Last in Sequence for more
details.
Some system applications are sensitive to sources of
analog noise. Spartan-3E FPGA circuitry is fully static and
does not employ internal charge pumps.
The CCLK configuration clock is active during the FPGA
configuration process. After configuration completes, the
CCLK oscillator is automatically disabled unless the
Bitstream Generator (BitGen) option Persist=Yes.
When all three supplies are valid, the minimum current
required to power-on the FPGA equals the worst-case
quiescent current, specified in Table 79. Spartan-3E FPGAs
DS312 (v4.2) December 14, 2018
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Product Specification
111
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