Spartan-3E FPGA Family: Functional Description
Description
Table 69: Spartan-3E FPGA Bitstream Generator (BitGen) Options (Cont’d)
Pins/Function
Affected
Values
(default)
Option Name
DriveDone
DONE pin
No
When configuration completes, the DONE pin stops driving Low and relies on an
external 330 Ω pull-up resistor to VCCAUX for a valid logic High.
Yes
When configuration completes, the DONE pin actively drives High. When using this
option, an external pull-up resistor is no longer required. Only one device in an FPGA
daisy-chain should use this setting.
DonePipe
ProgPin
DONE pin
No
The input path from DONE pin input back to the Startup sequencer is not pipelined.
Yes
This option adds a pipeline register stage between the DONE pin input and the Startup
sequencer. Used for high-speed daisy-chain configurations when DONE cannot rise in
a single CCLK cycle. Releases GWE and GTS signals on the first rising edge of
StartupClk after the DONE pin input goes High.
PROG_B pin
Pullup
Internally connects a pull-up resistor or between PROG_B pin and VCCAUX. An external
4.7 kΩ pull-up resistor to VCCAUX is still recommended since the internal pull-up value
may be weaker (see Table 78).
Pullnone No internal pull-up resistor on PROG_B pin. An external 4.7 kΩ pull-up resistor to
VCCAUX is required.
TckPin
TdiPin
TdoPin
TmsPin
JTAG TCK pin
JTAG TDI pin
JTAG TDO pin
JTAG TMS pin
Pullup
Internally connects a pull-up resistor between JTAG TCK pin and VCCAUX.
Pulldown Internally connects a pull-down resistor between JTAG TCK pin and GND.
Pullnone No internal pull-up resistor on JTAG TCK pin.
Pullup
Internally connects a pull-up resistor between JTAG TDI pin and VCCAUX.
Pulldown Internally connects a pull-down resistor between JTAG TDI pin and GND.
Pullnone No internal pull-up resistor on JTAG TDI pin.
Pullup
Internally connects a pull-up resistor between JTAG TDO pin and VCCAUX.
Pulldown Internally connects a pull-down resistor between JTAG TDO pin and GND.
Pullnone No internal pull-up resistor on JTAG TDO pin.
Pullup
Internally connects a pull-up resistor between JTAG TMS pin and VCCAUX.
Pulldown Internally connects a pull-down resistor between JTAG TMS pin and GND.
Pullnone No internal pull-up resistor on JTAG TMS pin.
UserID
JTAG User ID User string The 32-bit JTAG User ID register value is loaded during configuration. The default value
register
is all ones, 0xFFFF_FFFFhexadecimal. To specify another value, enter an 8-character
hexadecimal value.
Security
JTAG,
SelectMAP,
Readback,
Partial
None
Readback and limited partial reconfiguration are available via the JTAG port or via the
SelectMAP interface, if the Persist option is set to Yes.
Level1
Readback function is disabled. Limited partial reconfiguration is still available via the
JTAG port or via the SelectMAP interface, if the Persist option is set to Yes.
reconfiguration
Level2
Readback function is disabled. Limited partial reconfiguration is disabled.
CRC
Configuration
Enable
Default. Enable CRC checking on the FPGA bitstream. If error detected, FPGA asserts
INIT_B Low and DONE pin stays Low.
Disable
No
Turn off CRC checking.
Persist
SelectMAP
interface pins,
BPI mode,
Slave mode,
Configuration
All BPI and Slave mode configuration pins are available as user-I/O after configuration.
Yes
This option is required for Readback and partial reconfiguration using the SelectMAP
interface. The SelectMAP interface pins (see Slave Parallel Mode) are reserved after
configuration and are not available as user-I/O.
DS312 (v4.2) December 14, 2018
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Product Specification
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XILINX [ XILINX, INC ]
