Spartan-3E FPGA Family: Functional Description
X-Ref Target - Figure 67
Set PROG_B Low
after Power-On
Power-On
VCCINT >1V
and VCCAUX > 2V
No
and VCCO Bank 2 > 1V
Load
JPROG
instruction
Yes
Clear
configuration
memory
Yes
PROG_B = Low
No
No
INIT_B = High?
Yes
Sample
mode pins
(JTAG port becomes
available)
Load CFG_IN
instruction
Load configuration
data frames
No
CRC
correct?
INIT_B goes Low.
Abort Start-Up
Yes
Synchronous
TAP reset
(Clock five 1's
on TMS)
Load JSTART
instruction
Start-Up
sequence
User mode
No
Yes
Reconfigure?
DS312-2_59_051706
Figure 67: Boundary-Scan Configuration Flow Diagram
DS312 (v4.2) December 14, 2018
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Product Specification
105
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