R
Pinout Descriptions
Table 10: CP132 Package Pinout
Table 10: CP132 Package Pinout
XC3S250E
XC3S500E
Pin Name
XC3S250E
XC3S500E
Pin Name
CP132
Ball
CP132
Bank
Type
DUAL
VREF
DUAL
DUAL
DUAL
DUAL
Bank
Ball
B2
C2
C3
D1
D2
F2
Type
I/O
2
2
2
2
2
2
2
IO/M1
N7
P11
N1
M2
N2
P1
3
3
IO_L01P_3
IO/VREF_2
IO_L02N_3
IO_L02P_3
IO_L03N_3
IO_L03P_3
IO_L04N_3/LHCLK1
IO_L04P_3/LHCLK0
IO_L05N_3/LHCLK3/IRDY2
IO_L05P_3/LHCLK2
IO_L06N_3/LHCLK5
IO_L06P_3/LHCLK4/TRDY2
IO_L07N_3/LHCLK7
IO_L07P_3/LHCLK6
IO_L08N_3
IO_L08P_3
IO_L09N_3
IO_L09P_3
IP/VREF_3
VCCO_3
I/O
IO_L01N_2/INIT_B
IO_L01P_2/CSO_B
IO_L02N_2/MOSI/CSI_B
IO_L02P_2/DOUT/BUSY
IO_L03N_2/D6/GCLK13
3
I/O
3
I/O
3
I/O
3
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
I/O
N4
DUAL/
GCLK
3
F3
3
G1
F1
2
2
2
2
2
IO_L03P_2/D7/GCLK12
IO_L04N_2/D3/GCLK15
IO_L04P_2/D4/GCLK14
IO_L06N_2/D1/GCLK3
IO_L06P_2/D2/GCLK2
M4
N5
M5
P7
P6
DUAL/
GCLK
3
3
H1
G3
H3
H2
L2
DUAL/
GCLK
3
DUAL/
GCLK
3
3
DUAL/
GCLK
3
3
L1
I/O
DUAL/
GCLK
3
M1
L3
I/O
2
2
2
2
2
2
2
2
2
2
2
2
IO_L07N_2/DIN/D0
IO_L07P_2/M0
N8
P8
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
VREF
3
I/O
3
E2
E1
J2
VREF
VCCO
VCCO
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
IO_L08N_2/A22
M9
3
IO_L08P_2/A23
N9
3
VCCO_3
IO_L09N_2/A20
M10
N10
M11
N11
N12
P12
N3
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
A4
A8
C1
C7
C10
E3
E14
G2
H14
J1
IO_L09P_2/A21
GND
IO_L10N_2/VS1/A18
IO_L10P_2/VS2/A19
IO_L11N_2/CCLK
IO_L11P_2/VS0/A17
IP/VREF_2
GND
GND
GND
GND
GND
IP_L05N_2/M2/GCLK1
N6
DUAL/
GCLK
GND
GND
2
IP_L05P_2/RDWR_B/
GCLK0
M6
DUAL/
GCLK
GND
2
2
3
3
3
VCCO_2
VCCO_2
IO
M8
P3
J3
VCCO
VCCO
I/O
GND
K12
M3
M7
P5
GND
GND
IO/VREF_3
IO_L01N_3
K3
B1
VREF
I/O
GND
DS312-4 (v1.1) March 21, 2005
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11
Advance Product Specification
XILINX [ XILINX, INC ]
