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Pinout Descriptions
Table 10: CP132 Package Pinout
CP132: 132-ball Chip-scale Package
XC3S250E
XC3S500E
The XC3S250E and the XC3S500E FPGAs are available in
the 132-lead chip-scale package, CP132. Both devices
share a common footprint for this package as shown in
Table 10 and Figure 3.
CP132
Ball
Bank
Pin Name
IP_L06N_0/GCLK9
IP_L06P_0/GCLK8
VCCO_0
Type
GCLK
GCLK
VCCO
VCCO
DUAL
VREF
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
0
0
0
0
1
1
1
1
1
1
1
1
1
C8
B8
Table 10 lists all the CP132 package pins. They are sorted
by bank number and then by pin name. Pins that form a dif-
ferential I/O pair appear together in the table. The table also
shows the pin number for each pin and the pin type, as
defined earlier.
A6
VCCO_0
B10
F12
K13
N14
N13
M13
M12
L14
L13
J12
IO/A0
Physically, the D14 and K2 balls on the XC3S250E FPGA
are not connected but should be connected to VCCINT to
maintain density migration compatibility.
IO/VREF_1
IO_L01N_1/A15
IO_L01P_1/A16
IO_L02N_1/A13
IO_L02P_1/A14
IO_L03N_1/A11
IO_L03P_1/A12
IO_L04N_1/A9/RHCLK1
An electronic version of this package pinout table and foot-
print diagram is available for download from the Xilinx web-
site at http://www.xilinx.com/bvdocs/publications/s3e_pin.zip
.
Pinout Table
Table 10: CP132 Package Pinout
XC3S250E
XC3S500E
Pin Name
RHCLK/
DUAL
CP132
Ball
Bank
0
Type
I/O
1
1
1
1
1
1
1
IO_L04P_1/A10/RHCLK0
K14
J14
RHCLK/
DUAL
IO_L01N_0
C12
A13
A12
B12
B11
C11
C9
0
IO_L01P_0
I/O
IO_L05N_1/A7/RHCLK3/
TRDY1
RHCLK/
DUAL
0
IO_L02N_0
I/O
IO_L05P_1/A8/RHCLK2
J13
RHCLK/
DUAL
0
IO_L02P_0
I/O
0
IO_L03N_0/VREF_0
IO_L03P_0
VREF
I/O
IO_L06N_1/A5/RHCLK5
H12
H13
G13
G14
RHCLK/
DUAL
0
0
IO_L04N_0/GCLK5
IO_L04P_0/GCLK4
IO_L05N_0/GCLK7
IO_L05P_0/GCLK6
IO_L07N_0/GCLK11
IO_L07P_0/GCLK10
IO_L08N_0/VREF_0
IO_L08P_0
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
VREF
I/O
IO_L06P_1/A6/RHCLK4/
IRDY1
RHCLK/
DUAL
0
A10
A9
IO_L07N_1/A3/RHCLK7
RHCLK/
DUAL
0
0
B9
IO_L07P_1/A4/RHCLK6
RHCLK/
DUAL
0
B7
1
1
1
1
1
1
1
1
1
2
IO_L08N_1/A1
IO_L08P_1/A2
IO_L09N_1/LDC0
IO_L09P_1/HDC
IO_L10N_1/LDC2
IO_L10P_1/LDC1
IP/VREF_1
F13
F14
D12
D13
C13
C14
G12
E13
M14
P4
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
VREF
VCCO
VCCO
DUAL
0
A7
0
C6
0
B6
0
IO_L09N_0
C5
I/O
0
IO_L09P_0
B5
I/O
0
IO_L10N_0
C4
I/O
0
IO_L10P_0
B4
I/O
VCCO_1
0
IO_L11N_0/HSWAP
IO_L11P_0
B3
DUAL
I/O
VCCO_1
0
A3
IO/D5
10
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DS312-4 (v1.1) March 21, 2005
Advance Product Specification
XILINX [ XILINX, INC ]
