R
Pinout Descriptions
Table 10: CP132 Package Pinout
Table 10: CP132 Package Pinout
XC3S250E
XC3S500E
Pin Name
XC3S250E
XC3S500E
Pin Name
CP132
Ball
CP132
Ball
Bank
GND
GND
Type
GND
Bank
Type
GND
GND
P10
P14
P13
A1
VCCAUX VCCAUX
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
P9
A11
D3
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
GND
VCCAUX DONE
VCCAUX PROG_B
VCCAUX TCK
CONFIG
CONFIG
JTAG
D14
K2
B13
A2
VCCAUX TDI
JTAG
L12
P2
VCCAUX TDO
A14
B14
A5
JTAG
VCCAUX TMS
JTAG
User I/Os by Bank
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX
VCCAUX
VCCAUX
Table 20 indicates how the 92 available user-I/O pins are
distributed between the four I/O banks on the CP132 pack-
age.
E12
K1
Table 11: User I/Os Per Bank for the XC3S250E and XC3S500E in the CP132 Package
All Possible I/O Pins by Type
Package
Edge
Maximum
I/O
I/O Bank
I/O
11
0
INPUT
DUAL
1
VREF
GCLK
Top
0
1
2
3
22
23
26
21
92
0
0
0
0
0
2
2
2
2
8
8
0
Right
21
24
0
Bottom
Left
0
0
11
22
8
TOTAL
46
16
migrate between the XC3S250E and XC3S500E without
further consideration.
Footprint Migration Differences
The production XC3S250E and XC3S500E FPGAs have
identical footprints in the CP132 package. Designs can
12
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DS312-4 (v1.1) March 21, 2005
Advance Product Specification
XILINX [ XILINX, INC ]
