R
Pinout Descriptions
User I/Os by Bank
Table 8 indicates how the 66 available user-I/O pins are dis-
tributed between the four I/O banks on the VQ100 package.
Table 8: User I/Os Per Bank for XC3S100E and XC3S250E in the VQ100 Package
All Possible I/O Pins by Type
Package
Edge
Maximum
I/O
I/O Bank
I/O
5
INPUT
DUAL
VREF
GCLK
Top
0
1
2
3
15
15
19
17
66
0
0
0
1
1
1
0
1
1
1
1
4
8
8
Right
Bottom
Left
6
0
18
2
0
5
8
TOTAL
16
21
24
Footprint Migration Differences
Table 9: XC3S100E Pinout Changes between
Production Devices and Engineering Samples
The production XC3S100E and XC3S250E FPGAs have
identical footprints in the VQ100 package. Designs can
migrate between the XC3S100E and XC3S250E without
further consideration.
XC3S100E
Production
Devices
XC3S100E
Engineering
Samples
VQ100 Pin
P40
The pinout changed slightly between the XC3S100E engi-
neering samples and the production devices, as shown in
Table 9. In the engineering samples, the mode select pins
M1 and M0 overlap with two global clock inputs feeding the
bottom-edge global buffers and DCMs. In the production
devices, the mode pins are swapped with parallel mode
data pins, D1 and D2. This way, these two mode pins do not
interfere with global clock inputs.
D2/GCLK2
D1/GCLK3
M1
M1/GCLK2
M0/GCLK3
D2
P41
P42
P43
M0
D1
8
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DS312-4 (v1.1) March 21, 2005
Advance Product Specification
XILINX [ XILINX, INC ]
