R
Pinout Descriptions
VQ100 Footprint
In Figure 2, note pin 1 indicator in top-left corner and logo
orientation. The engineering sample footprint is slightly dif-
ferent.
PROG_B
IO_L01P_3
1
2
75 TMS
74 VCCAUX
Bank 0
IO_L01N_3
IO_L02P_3
3
4
5
6
7
8
9
73 VCCO_1
72 GND
IO_L02N_3/VREF_3
VCCINT
71 IO_L07N_1
70 IO_L07P_1
69 IP/VREF_1
GND
VCCO_3
68 IO_L06N_1/RHCLK7
67 IO_L06P_1/RHCLK6
66 IO_L05N_1/RHCLK5
65 IO_L05P_1/RHCLK4
64 GND
IO_L03P_3/LHCLK0
IO_L03N_3/LHCLK1 10
IO_L04P_3/LHCLK2 11
IO_L04N_3/LHCLK3 12
IP 13
63 IO_L04N_1/RHCLK3
62 IO_L04P_1/RHCLK2
61 IO_L03N_1/RHCLK1
60 IO_L03P_1/RHCLK0
59 GND
GND 14
IO_L05P_3/LHCLK4 15
IO_L05N_3/LHCLK5 16
IO_L06P_3/LHCLK6 17
IO_L06N_3/LHCLK7 18
GND 19
58 IO_L02N_1
57 IO_L02P_1
VCCO_3 20
56 VCCINT
VCCAUX 21
55 VCCO_1
IO_L07P_3 22
54 IO_L01N_1
IO_L07N_3 23
53 IO_L01P_1
IO_L01P_2/CSO_B 24
IO_L01N_2/INIT_B 25
52 GND
Bank 2
51 DONE
DS312-4_02_030705
Figure 2: VQ100 Package Production Footprint (top view). Engineering Samples have slightly different footprint.
I/O: Unrestricted,
general-purpose user I/O
DUAL: Configuration pin, then
possible user-I/O
VREF: User I/O or input
voltage reference for bank
16
1
21
24
4
4
8
4
4
INPUT: Unrestricted,
general-purpose input pin
GCLK: User I/O, input, or
global buffer input
VCCO: Output voltage supply
for bank
CONFIG: Dedicated
configuration pins
JTAG: Dedicated JTAG port
pins
VCCINT: Internal core supply
voltage (+1.2V)
2
N.C.: Not connected
GND: Ground
VCCAUX: Auxiliary supply
voltage (+2.5V)
0
12
DS312-4 (v1.1) March 21, 2005
www.xilinx.com
9
Advance Product Specification
XILINX [ XILINX, INC ]
