R
Pinout Descriptions
Table 7: VQ100 Package Pinout
VQ100: 100-lead Very-thin Quad Flat
Package
The XC3S100E and the XC3S250E devices are available in
the 100-lead very-thin quad flat package, VQ100. Both
devices share a common footprint for this package as
shown in Table 7 and Figure 2.
XC3S100E
XC3S250E
VQ100
Pin
Bank
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Pin Name
Number
Type
VCCO
I/O
VCCO_0
P97
P54
P53
P58
P57
P61
P60
P63
P62
P66
P65
P68
P67
P71
P70
P69
P55
P73
P34
P42
P25
P24
P27
P26
P33
P32
P36
P35
P41
P40
P44
P43
P48
P47
IO_L01N_1
Table 7 lists all the package pins. They are sorted by bank
number and then by pin name of the largest device. Pins
that form a differential I/O pair appear together in the table.
The table also shows the pin number for each pin and the
pin type, as defined earlier.
IO_L01P_1
I/O
IO_L02N_1
I/O
IO_L02P_1
I/O
IO_L03N_1/RHCLK1
IO_L03P_1/RHCLK0
IO_L04N_1/RHCLK3
IO_L04P_1/RHCLK2
IO_L05N_1/RHCLK5
IO_L05P_1/RHCLK4
IO_L06N_1/RHCLK7
IO_L06P_1/RHCLK6
IO_L07N_1
RHCLK
RHCLK
RHCLK
RHCLK
RHCLK
RHCLK
RHCLK
RHCLK
I/O
The VQ100 package does not support the Byte-wide
Peripheral Interface (BPI) configuration mode. Conse-
quently, the VQ100 footprint has fewer DUAL-type pins than
other packages.
An electronic version of this package pinout table and foot-
print diagram is available for download from the Xilinx web
site at http://www.xilinx.com/bvdocs/publications/s3e_pin.zip.
Pinout Table
Table 7 shows the pinout for production Spartan-3E FPGAs
in the VQ100 package. The XC3S100 engineering samples
have a slightly different pinout, as described in Table 9.
IO_L07P_1
I/O
Table 7: VQ100 Package Pinout
IP/VREF_1
VREF
VCCO
VCCO
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
XC3S100E
XC3S250E
Pin Name
VQ100
Pin
Number
VCCO_1
Bank
Type
I/O
VCCO_1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IO
P92
P79
P78
P84
P83
P86
P85
P91
P90
P95
P94
P99
P98
P89
P88
P82
IO/D5
IO_L01N_0
I/O
IO/M1
IO_L01P_0
I/O
IO_L01N_2/INIT_B
IO_L01P_2/CSO_B
IO_L02N_2/MOSI/CSI_B
IO_L02P_2/DOUT/BUSY
IO_L03N_2/D6/GCLK13
IO_L03P_2/D7/GCLK12
IO_L04N_2/D3/GCLK15
IO_L04P_2/D4/GCLK14
IO_L06N_2/D1/GCLK3
IO_L06P_2/D2/GCLK2
IO_L07N_2/DIN/D0
IO_L07P_2/M0
IO_L02N_0/GCLK5
IO_L02P_0/GCLK4
IO_L03N_0/GCLK7
IO_L03P_0/GCLK6
IO_L05N_0/GCLK11
IO_L05P_0/GCLK10
IO_L06N_0/VREF_0
IO_L06P_0
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
VREF
I/O
DUAL/GCLK
DUAL/GCLK
DUAL/GCLK
DUAL/GCLK
DUAL/GCLK
DUAL/GCLK
DUAL
IO_L07N_0/HSWAP
IO_L07P_0
DUAL
I/O
IP_L04N_0/GCLK9
IP_L04P_0/GCLK8
VCCO_0
GCLK
GCLK
VCCO
DUAL
IO_L08N_2/VS1
IO_L08P_2/VS2
DUAL
DUAL
6
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DS312-4 (v1.1) March 21, 2005
Advance Product Specification
XILINX [ XILINX, INC ]
