R
Spartan-IIE FPGA Family: DC and Switching Characteristics
(1)
IOB Input Switching Characteristics
Input delays associated with the pad are specified for LVTTL levels. For other standards, adjust the delays with the values
shown in IOB Input Delay Adjustments for Different Standards, page 38.
Speed Grade
-7
-6
Symbol
Propagation Delays
TIOPI
Description
Device
Min
Max
Min
Max Units
Pad to I output, no delay
Pad to I output, with delay
All
All
All
0.4
0.5
0.7
0.8
1.0
1.5
0.4
0.5
0.7
0.8
1.0
1.6
ns
ns
ns
TIOPID
TIOPLI
Pad to output IQ via transparent latch,
no delay
TIOPLID
Pad to output IQ via transparent latch,
with delay
XC2S50E
XC2S100E
XC2S150E
XC2S200E
XC2S300E
XC2S400E
XC2S600E
1.3
1.3
1.3
1.3
1.3
1.4
1.5
3.0
3.0
3.2
3.2
3.2
3.2
3.5
1.3
1.3
1.3
1.3
1.3
1.4
1.5
3.1
3.1
3.3
3.3
3.3
3.4
3.7
ns
ns
ns
ns
ns
ns
ns
Sequential Delays
TIOCKIQ
Clock CLK to output IQ
All
0.1
0.7
0.1
0.7
ns
Setup/Hold Times with Respect to Clock CLK
TIOPICK / TIOICKP Pad, no delay
All
1.4 / 0
2.9 / 0
2.9 / 0
3.1 / 0
3.1 / 0
3.1 / 0
3.2 / 0
3.5 / 0
0.7 / 0.01
-
-
-
-
-
-
-
-
-
1.5 / 0
2.9 / 0
2.9 / 0
3.1 / 0
3.1 / 0
3.1 / 0
3.2 / 0
3.5 / 0
0.7 / 0.01
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
TIOPICKD / TIOICKPD Pad, with delay
XC2S50E
XC2S100E
XC2S150E
XC2S200E
XC2S300E
XC2S400E
XC2S600E
All
TIOICECK / TIOCKICE ICE input
Set/Reset Delays
TIOSRCKI
TIOSRIQ
TGSRQ
SR input (IFF, synchronous)
SR input to IQ (asynchronous)
GSR to output IQ
All
All
All
0.9
0.5
3.8
-
1.0
0.5
3.8
-
ns
ns
ns
1.2
8.5
1.4
9.7
Notes:
1. Input timing for LVTTL is measured at 1.4V. For other I/O standards, see the table Delay Measurement Methodology, page 41.
DS077-3 (v2.3) June 18, 2008
www.xilinx.com
37
Product Specification
XILINX [ XILINX, INC ]
