R
Spartan-IIE FPGA Family: DC and Switching Characteristics
Power-On Requirements
Spartan®-IIE FPGAs require that a minimum supply current
ICCPO be provided to the VCCINT lines for a successful
power-on. If more current is available, the FPGA can con-
sume more than ICCPO min., though this cannot adversely
affect reliability.
A maximum limit for ICCPO is not specified. Be careful when
using foldback/crowbar supplies and fuses. It is possible to
control the magnitude of ICCPO by limiting the supply current
available to the FPGA. A current limit below the trip level will
avoid inadvertently activating over-current protection cir-
cuits.
Symbol
Description
Min(1)
300
Typ
Max
Units
mA
ICCPO
Total VCCINT supplycurrent Commercial XC2S50E - XC2S300E After PCN(2)
-
-
-
-
required during power-on
Before
PCN(2)
500
mA
XC2S400E - XC2S600E
500
500
2
-
-
-
-
-
-
mA
mA
A
Industrial
XC2S50E - XC2S300E After PCN(2)
Before
PCN(2)
XC2S400E - XC2S600E
After PCN(2)
700
500
2
-
-
-
mA
μs
TCCPO VCCINT(3,4) ramp time
-
Before PCN(2)
-
50
-
ms
μA
IHSPO
AC current per pin during power-on in
hot-swap applications when
After PCN(2)
-
60
VIN > VCCO + 0.4V; duration < 10ns
Notes:
1. The ICCPO requirement applies for a brief time (commonly only a few milliseconds) when VCCINT ramps from 0 to 1.8V.
2. Devices built after the Product Change Notice PCN 2002-05 (see
http://www.xilinx.com/support/documentation/customer_notices/pcn2002-05.pdf) have improved power-on requirements. Devices
after the PCN have a ‘T’ preceding the date code as referenced in the PCN. Note that the XC2S150E, XC2S400E, and XC2S600E
always have this mark. Devices before the PCN have an ‘S’ preceding the date code. Note that devices before the PCN are
measured with VCCINT and VCCO powering up simultaneously.
3. The ramp time is measured from GND to 1.8V on a fully loaded board.
4. VCCINT must not dip in the negative direction during power on.
5. I/Os are not guaranteed to be disabled until VCCINT is applied.
6. For more information on designing to meet the power-on specifications, refer to the application note XAPP450 "Power-On Current
Requirements for the Spartan-II and Spartan-IIE Families".
DC Input and Output Levels
Values for VIL and VIH are recommended input voltages.
Values for VOL and VOH are guaranteed output voltages
over the recommended operating conditions. Only selected
standards are tested. These are chosen to ensure that all
standards meet their specifications. The selected standards
are tested at minimum VCCO with the respective IOL and IOH
currents shown. Other standards are sample tested.
VIL
VIH
VOL
V, Max
0.4
VOH
V, Min
2.4
IOL
mA
24
12
8
IOH
mA
–24
–12
–8
Input/Output
Standard
V, Min
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
V, Max
0.8
V, Min
2.0
V, Max
3.6
LVTTL(1)
LVCMOS2
LVCMOS18
PCI, 3.3V
GTL
0.7
1.7
2.7
0.4
1.9
35% VCCO
30% VCCO
65% VCCO
50% VCCO
1.95
0.4
VCCO – 0.4
VCCO + 0.5
3.6
10% VCCO
0.4
90% VCCO Note (2) Note (2)
VREF – 0.05 VREF + 0.05
VREF – 0.1 VREF + 0.1
-
-
40
36
-
-
GTL+
3.6
0.6
DS077-3 (v2.3) June 18, 2008
www.xilinx.com
33
Product Specification
XILINX [ XILINX, INC ]
