R
Spartan-IIE FPGA Family: DC and Switching Characteristics
IOB Output Switching Characteristics
Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust
the delays with the values shown in IOB Output Delay Adjustments for Different Standards(1), page 40.
Speed Grade
-7
-6
Symbol
Propagation Delays
TIOOP
Description
Min
Max
Min
Max
Units
O input to pad
1.0
1.2
2.7
3.1
1.0
1.2
2.9
3.4
ns
ns
TIOOLP
O input to pad via transparent latch
3-state Delays
TIOTHZ
T input to pad high impedance(1)
0.7
1.1
0.8
1.2
1.9
1.7
2.9
2.0
3.2
4.6
0.7
1.1
0.8
1.2
1.9
1.9
3.1
2.2
3.4
4.9
ns
ns
ns
ns
ns
TIOTON
T input to valid data on pad
TIOTLPHZ
T input to pad high impedance via transparent latch(1)
T input to valid data on pad via transparent latch
GTS to pad high impedance(1)
TIOTLPON
TGTS
Sequential Delays
TIOCKP
Clock CLK to pad
0.9
0.7
1.1
2.8
2.0
3.2
0.9
0.7
1.1
2.9
2.2
3.4
ns
ns
ns
TIOCKHZ
Clock CLK to pad high impedance (synchronous)(1)
Clock CLK to valid data on pad (synchronous)
TIOCKON
Setup/Hold Times with Respect to Clock CLK
TIOOCK / TIOCKO O input
1.0 / 0
0.7 / 0
0.9 / 0
0.6 / 0
0.6 / 0
0.9 / 0
-
-
-
-
-
-
1.1 / 0
0.7 / 0
1.0 / 0
0.7 / 0
0.8 / 0
1.0 / 0
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
TIOOCECK / TIOCKOCE OCE input
TIOSRCKO / TIOCKOSR SR input (OFF)
TIOTCK / TIOCKT
3-state setup times, T input
TIOTCECK / TIOCKTCE 3-state setup times, TCE input
TIOSRCKT / TIOCKTSR 3-state setup times, SR input (TFF)
Set/Reset Delays
TIOSRP
TIOSRHZ
TIOSRON
TIOGSRQ
SR input to pad (asynchronous)
SR input to pad high impedance (asynchronous)(1)
SR input to valid data on pad (asynchronous)
GSR to pad
1.2
1.0
1.4
3.8
3.3
2.4
3.7
8.5
1.2
1.0
1.4
3.8
3.5
2.7
3.9
9.7
ns
ns
ns
ns
Notes:
1. Three-state turn-off delays should not be adjusted.
DS077-3 (v2.3) June 18, 2008
www.xilinx.com
39
Product Specification
XILINX [ XILINX, INC ]
