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XC2S400E-6FG456C 参数 Datasheet PDF下载

XC2S400E-6FG456C图片预览
型号: XC2S400E-6FG456C
PDF下载: 下载PDF文件 查看货源
内容描述: 的Spartan- IIE FPGA [Spartan-IIE FPGA]
分类和应用:
文件页数/大小: 108 页 / 5063 K
品牌: XILINX [ XILINX, INC ]
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R
Spartan-IIE FPGA Family: DC and Switching Characteristics  
Calculation of T  
Capacitance  
as a Function of  
Constants for Calculating T  
IOOP  
IOOP  
(1)  
CSL  
FL  
TIOOP is the propagation delay from the O Input of the IOB  
to the pad. The values for TIOOP are based on the standard  
capacitive load (CSL) for each I/O standard as listed in the  
table Constants for Calculating TIOOP, below.  
Standard  
(pF)  
35  
35  
35  
35  
35  
35  
35  
35  
35  
35  
35  
35  
35  
35  
35  
35  
10  
10  
0
(ns/pF)  
LVTTL Fast Slew Rate, 2 mA drive  
LVTTL Fast Slew Rate, 4 mA drive  
LVTTL Fast Slew Rate, 6 mA drive  
LVTTL Fast Slew Rate, 8 mA drive  
0.41  
0.20  
For other capacitive loads, use the formulas below to calcu-  
0.13  
late an adjusted propagation delay, TIOOP1  
.
0.079  
0.044  
0.043  
0.033  
0.41  
TIOOP1 = TIOOP + Adj + (CLOAD – CSL) * FL  
LVTTL Fast Slew Rate, 12 mA drive  
LVTTL Fast Slew Rate, 16 mA drive  
LVTTL Fast Slew Rate, 24 mA drive  
LVTTL Slow Slew Rate, 2 mA drive  
LVTTL Slow Slew Rate, 4 mA drive  
LVTTL Slow Slew Rate, 6 mA drive  
LVTTL Slow Slew Rate, 8 mA drive  
LVTTL Slow Slew Rate, 12 mA drive  
LVTTL Slow Slew Rate, 16 mA drive  
LVTTL Slow Slew Rate, 24 mA drive  
LVCMOS2  
Where:  
Adj  
is selected from IOB Output Delay Adjustments  
for Different Standards(1), page 40, according  
to the I/O standard used  
CLOAD is the capacitive load for the design  
FL is the capacitance scaling factor  
0.20  
0.100  
0.086  
0.058  
0.050  
0.048  
0.041  
0.050  
0.050  
0.033  
0.014  
0.017  
0.022  
0.016  
0.014  
0.028  
0.016  
0.029  
0.016  
0.035  
0.037  
Delay Measurement Methodology  
VREF  
Point Typ(2)  
Meas.  
(1)  
(1)  
Standard  
LVTTL  
VL  
VH  
0
3
1.4  
-
LVCMOS2  
PCI33_3  
PCI66_3  
GTL  
0
2.5  
1.125  
-
LVCMOS18  
Per PCI Spec  
Per PCI Spec  
-
PCI 33 MHz 3.3V  
-
PCI 66 MHz 3.3V  
VREF – 0.2 VREF + 0.2 VREF  
VREF – 0.2 VREF + 0.2 VREF  
0.80  
1.0  
0.75  
0.90  
0.90  
1.5  
1.25  
1.5  
GTL  
GTL+  
GTL+  
0
HSTL Class I VREF – 0.5 VREF + 0.5 VREF  
HSTL Class III VREF – 0.5 VREF + 0.5 VREF  
HSTL Class IV VREF – 0.5 VREF + 0.5 VREF  
SSTL3 I and II VREF – 1.0 VREF + 1.0 VREF  
SSTL2 I and II VREF – 0.75 VREF + 0.75 VREF  
HSTL Class I  
20  
20  
20  
30  
30  
30  
30  
20  
10  
HSTL Class III  
HSTL Class IV  
SSTL2 Class I  
SSTL2 Class II  
CTT  
AGP  
VREF – 0.2 VREF + 0.2 VREF  
VREF VREF VREF  
(0.2xVCCO) (0.2xVCCO  
1.2 – 0.125 1.2 + 0.125 1.2  
1.6 – 0.3 1.6 + 0.3 1.6  
SSTL3 Class I  
+
Per AGP  
Spec  
SSTL3 Class II  
)
CTT  
LVDS  
AGP  
LVPECL  
Notes:  
Notes:  
1. I/O parameter measurements are made with the capacitance  
values shown above. Refer to Application Note XAPP179 for  
appropriate terminations.  
1. Input waveform switches between VL and VH.  
2. Measurements are made at VREF Typ, Maximum, and  
Minimum. Worst-case values are reported.  
2. I/O standard measurements are reflected in the IBIS model  
3. I/O parameter measurements are made with the capacitance  
values shown in the following table, Constants for Calculating  
TIOOP. Refer to Application Note XAPP179 for appropriate  
terminations.  
information except where the IBIS format precludes it.  
4. I/O standard measurements are reflected in the IBIS model  
information except where the IBIS format precludes it.  
DS077-3 (v2.3) June 18, 2008  
www.xilinx.com  
41  
Product Specification  
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