R
Spartan-IIE FPGA Family: DC and Switching Characteristics
IOB Input Delay Adjustments for Different Standards
Input delays associated with the pad are specified for LVTTL. For other standards, adjust the delays by the values shown. A
delay adjusted in this way constitutes a worst-case limit.
Speed Grade
Symbol
Description
Standard
-7
-6
Units
Data Input Delay Adjustments
TILVTTL
TILVCMOS2
TILVCMOS18
TILVDS
Standard-specific data input delay LVTTL
adjustments
0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LVCMOS2
0
0
LVCMOS18
LVDS
0.20
0.15
0.15
0.08
–0.11
0.14
0.14
0.04
0.04
0.04
0.10
0.04
0.20
0.15
0.15
0.08
–0.11
0.14
0.14
0.04
0.04
0.04
0.10
0.04
TILVPECL
TIPCI33_3
TIPCI66_3
TIGTL
LVPECL
PCI, 33 MHz, 3.3V
PCI, 66 MHz, 3.3V
GTL
TIGTLP
GTL+
TIHSTL
HSTL
TISSTL2
TISSTL3
TICTT
SSTL2
SSTL3
CTT
TIAGP
AGP
38
www.xilinx.com
DS077-3 (v2.3) June 18, 2008
Product Specification
XILINX [ XILINX, INC ]
