R
Spartan-IIE FPGA Family: DC and Switching Characteristics
Switching Characteristics
Internal timing parameters are derived from measuring
internal test patterns. Listed below are representative val-
ues. For more specific, more precise, and worst-case guar-
anteed data, use the values reported by the static timing
analyzer (TRACE in the Xilinx Development System) and
back-annotated to the simulation netlist. All timing parame-
ters assume worst-case operating conditions (supply volt-
age and junction temperature). Values apply to all
Spartan-IIE devices unless otherwise noted.
(1)
Global Clock Input to Output Delay for LVTTL, with DLL (Pin-to-Pin)
Speed Grade
All
Min
1.0
-7
-6
Symbol
Description
Max
3.1
Max
3.1
Units
TICKOFDLL
LVTTL global clock input to output delay using
output flip-flop for LVTTL, 12 mA, fast slew rate,
with DLL.
ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2. Output timing is measured at 1.4V with 35 pF external capacitive load for LVTTL. The 35 pF load does not apply to the Min values.
For other I/O standards and different loads, see the tables Constants for Calculating TIOOP and Delay Measurement Methodology,
page 41.
3. DLL output jitter is already included in the timing calculation.
4. For data output with different standards, adjust delays with the values shown in IOB Output Delay Adjustments for Different
Standards(1), page 40. For a global clock input with standards other than LVTTL, adjust delays with values from the I/O Standard
Global Clock Input Adjustments, page 42.
(1)
Global Clock Input to Output Delay for LVTTL, without DLL (Pin-to-Pin)
Speed Grade
All
Min
1.5
1.5
1.5
1.5
1.5
1.5
1.6
-7
Max
4.4
4.4
4.5
4.5
4.5
4.6
4.7
-6
Max
4.6
4.6
4.7
4.7
4.7
4.8
4.9
Symbol
Description
Device
Units
ns
TICKOF
LVTTL global clock input to output
delay using output flip-flop for
LVTTL, 12 mA, fast slew rate,
without DLL.
XC2S50E
XC2S100E
XC2S150E
XC2S200E
XC2S300E
XC2S400E
XC2S600E
ns
ns
ns
ns
ns
ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2. Output timing is measured at 1.4V with 35 pF external capacitive load for LVTTL. The 35 pF load does not apply to the Min values.
For other I/O standards and different loads, see the tables Constants for Calculating TIOOP and Delay Measurement Methodology,
page 41.
3. For data output with different standards, adjust delays with the values shown in IOB Output Delay Adjustments for Different
Standards(1), page 40. For a global clock input with standards other than LVTTL, adjust delays with values from the I/O Standard
Global Clock Input Adjustments, page 42.
DS077-3 (v2.3) June 18, 2008
www.xilinx.com
35
Product Specification
XILINX [ XILINX, INC ]
