R
Spartan-IIE FPGA Family: DC and Switching Characteristics
IOB Output Delay Adjustments for Different Standards(1)
Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust
the delays by the values shown. A delay adjusted in this way constitutes a worst-case limit.
Speed Grade
Symbol
Description
Standard
-7
-6
Units
Output Delay Adjustments (Adj)
TOLVTTL_S2
TOLVTTL_S4
TOLVTTL_S6
TOLVTTL_S8
TOLVTTL_S12
TOLVTTL_S16
TOLVTTL_S24
TOLVTTL_F2
TOLVTTL_F4
TOLVTTL_F6
TOLVTTL_F8
TOLVTTL_F12
TOLVTTL_F16
TOLVTTL_F24
TOLVCMOS2
TOLVCMOS18
TOLVDS
Standard-specific adjustments for LVTTL, Slow, 2 mA
14.7
7.5
14.7
7.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
output delays terminating at pads
4 mA
(based on standard capacitive
6 mA
4.8
4.8
load, CSL
)
8 mA
3.0
3.0
12 mA
16 mA
24 mA
1.9
1.9
1.7
1.7
1.3
1.3
LVTTL, Fast, 2 mA
13.1
5.3
13.1
5.3
4 mA
6 mA
3.1
3.1
8 mA
1.0
1.0
12 mA
16 mA
24 mA
0
0
–0.05
–0.20
0.09
0.7
–0.05
–0.20
0.09
0.7
LVCMOS2
LVCMOS18
LVDS
–1.2
–0.41
2.3
–1.2
–0.41
2.3
TOLVPECL
TOPCI33_3
TOPCI66_3
TOGTL
LVPECL
PCI, 33 MHz, 3.3V
PCI, 66 MHz, 3.3V
GTL
–0.41
0.49
0.8
–0.41
0.49
0.8
TOGTLP
GTL+
TOHSTL_I
HSTL I
–0.51
–0.91
–1.01
–0.51
–0.91
–0.51
–1.01
–0.61
–0.91
–0.51
–0.91
–1.01
–0.51
–0.91
–0.51
–1.01
–0.61
–0.91
TOHSTL_III
TOHSTL_IV
TOSSTL2_I
TOSSLT2_II
TOSSTL3_I
TOSSTL3_II
TOCTT
HSTL III
HSTL IV
SSTL2 I
SSTL2 II
SSTL3 I
SSTL3 II
CTT
TOAGP
AGP
Notes:
1. Output timing is measured at 1.4V with 35 pF external capacitive load for LVTTL. For other I/O standards and different loads, see the
tables Constants for Calculating TIOOP and Delay Measurement Methodology, page 41.
40
www.xilinx.com
DS077-3 (v2.3) June 18, 2008
Product Specification
XILINX [ XILINX, INC ]
