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XC2S400E-6FG456C 参数 Datasheet PDF下载

XC2S400E-6FG456C图片预览
型号: XC2S400E-6FG456C
PDF下载: 下载PDF文件 查看货源
内容描述: 的Spartan- IIE FPGA [Spartan-IIE FPGA]
分类和应用:
文件页数/大小: 108 页 / 5063 K
品牌: XILINX [ XILINX, INC ]
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R
Spartan-IIE FPGA Family: DC and Switching Characteristics  
Global Clock Setup and Hold for LVTTL Standard, with DLL (Pin-to-Pin)  
Speed Grade  
-7  
-6  
Symbol  
Description  
Min  
Min  
Units  
TPSDLL / TPHDLL Input setup and hold time relative to global clock input signal  
1.6 / 0  
1.7 / 0  
ns  
for LVTTL standard, no delay, IFF,(1) with DLL  
Notes:  
1. IFF = Input Flip-Flop or Latch  
2. Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured  
relative to the Global Clock input signal with the slowest route and heaviest load.  
3. DLL output jitter is already included in the timing calculation.  
4. For data input with different standards, adjust the setup time delay by the values shown in IOB Input Delay Adjustments for Different  
Standards, page 38. For a global clock input with standards other than LVTTL, adjust delays with values from the I/O Standard  
Global Clock Input Adjustments, page 42.  
5. A zero hold time listing indicates no hold time or a negative hold time.  
Global Clock Setup and Hold for LVTTL Standard, without DLL (Pin-to-Pin)  
Speed Grade  
-7  
-6  
Symbol  
Description  
Device  
Min  
Min  
Units  
ns  
TPSFD / TPHFD  
Input setup and hold time relative  
to global clock input signal for  
LVTTL standard, with delay, IFF,(1)  
without DLL  
XC2S50E  
XC2S100E  
XC2S150E  
XC2S200E  
XC2S300E  
XC2S400E  
XC2S600E  
1.8 / 0  
1.8 / 0  
1.9 / 0  
1.9 / 0  
2.0 / 0  
2.0 / 0  
2.1 / 0  
1.8 / 0  
1.8 / 0  
1.9 / 0  
1.9 / 0  
2.0 / 0  
2.0 / 0  
2.1 / 0  
ns  
ns  
ns  
ns  
ns  
ns  
Notes:  
1. IFF = Input Flip-Flop or Latch  
2. Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured  
relative to the Global Clock input signal with the slowest route and heaviest load.  
3. For data input with different standards, adjust the setup time delay by the values shown in IOB Input Delay Adjustments for Different  
Standards, page 38. For a global clock input with standards other than LVTTL, adjust delays with values from the I/O Standard  
Global Clock Input Adjustments, page 42.  
36  
www.xilinx.com  
DS077-3 (v2.3) June 18, 2008  
Product Specification  
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