R
Spartan-IIE FPGA Family: DC and Switching Characteristics
Recommended Operating Conditions
Symbol
Description
Min
Max
85
Units
°C
°C
V
TJ
Junction temperature
Commercial
Industrial
0
–40
100
VCCINT
VCCO
TIN
Supply voltage relative to GND(1)
Supply voltage relative to GND(2)
Input signal transition time(3)
Commercial
Industrial
1.8 – 5%
1.8 – 5%
1.2
1.8 + 5%
1.8 + 5%
3.6
V
Commercial
Industrial
V
1.2
3.6
V
-
250
ns
Notes:
1. Functional operation is guaranteed down to a minimum VCCINT of 1.62V (Nominal VCCINT –10%). For every 50 mV reduction in
VCCINT below 1.71V (nominal VCCINT –5%), all delay parameters increase by approximately 3%.
2. Minimum and maximum values for VCCO vary according to the I/O standard selected.
3. Input and output measurement threshold is ~50% of VCCO. See Delay Measurement Methodology, page 41 for specific details.
DC Characteristics Over Operating Conditions
Symbol
Description
Min
Typ
Max
Units
VDRINT
Data retention VCCINT voltage (below which configuration data may
be lost)
1.5
-
-
V
VDRIO
Data retention VCCO voltage (below which configuration data may be
lost)
1.2
-
-
V
ICCINTQ
Quiescent VCCINT supply current(1)
XC2S50E
Commercial
Industrial
-
10
10
10
10
10
10
10
10
12
12
15
15
15
15
-
200
200
200
200
300
300
300
300
300
300
300
300
400
400
2
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
μA
-
XC2S100E Commercial
Industrial
-
-
XC2S150E Commercial
Industrial
-
-
XC2S200E Commercial
Industrial
-
-
XC2S300E Commercial
Industrial
-
-
XC2S400E Commercial
Industrial
-
-
XC2S600E Commercial
Industrial
-
-
ICCOQ
IREF
IL
Quiescent VCCO supply current(1)
VREF current per VREF pin
-
-
-
20
Input or output leakage current per pin
Input capacitance (sample tested)
–10
-
+10
8
μA
pF
CIN
TQ, PQ, FG, FT packages
-
-
-
IRPU
Pad pull-up (when selected) @ VIN = 0V, VCCO = 3.3V
(sample tested)(2)
-
0.25
mA
IRPD
Pad pull-down (when selected) @ VIN = 3.6V (sample tested)(2)
-
-
0.25
mA
Notes:
1. With no output current loads, no active input pull-up resistors, all I/O pins 3-stated and floating.
2. Internal pull-up and pull-down resistors guarantee valid logic levels at unconnected input pins. These pull-up and pull-down resistors
do not provide valid logic levels when input pins are connected to other circuits.
32
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DS077-3 (v2.3) June 18, 2008
Product Specification
XILINX [ XILINX, INC ]
