R
XC18V00 Series of In-System Programmable Configuration PROMs
serial vector format (SVF) files for use with any tools that
accept SVF format and with automatic test equipment.
cycles and a minimum data retention of 20 years. Each
device meets all functional, performance, and data retention
specifications within this endurance limit.
All outputs are held in a high-impedance state or held at
clamp levels during in-system programming.
Design Security
OE/RESET
The Xilinx in-system programmable PROM devices incorpo-
rate advanced data security features to fully protect the pro-
gramming data against unauthorized reading. Table 3
shows the security setting available.
The ISP programming algorithm requires issuance of a
reset that causes OE to go Low.
The read security bit can be set by the user to prevent the
internal programming pattern from being read or copied via
JTAG. When set, it allows device erase. Erasing the entire
device is the only way to reset the read security bit.
External Programming
Xilinx reprogrammable PROMs can also be programmed by
the Xilinx HW-130 device programmer. This provides the
added flexibility of using pre-programmed devices in board
design and boundary-scan manufacturing tools, with an
in-system programmable option for future enhancements
and design changes.
Table 3: Data Security Options
Default = Reset
Set
Read Allowed
Program/Erase Allowed
Read Inhibited via JTAG
Erase Allowed
Reliability and Endurance
Xilinx in-system programmable products provide a guaran-
teed endurance level of 20,000 in-system program/erase
(a)
(b)
DS026_02_011100
Figure 2: In-System Programming Operation (a) Solder Device to PCB and (b) Program Using Download Cable
IEEE 1149.1 Boundary-Scan (JTAG)
The XC18V00 family is fully compliant with the IEEE Std.
1149.1 Boundary-Scan, also known as JTAG. A Test
Access Port (TAP) and registers are provided to support all
required boundary scan instructions, as well as many of the
optional instructions specified by IEEE Std. 1149.1. In addi-
tion, the JTAG interface is used to implement in-system pro-
gramming (ISP) to facilitate configuration, erasure, and
verification operations on the XC18V00 device.
Table 4 lists the required and optional boundary-scan
instructions supported in the XC18V00. Refer to the IEEE
Std. 1149.1 specification for a complete description of
boundary-scan architecture and the required and optional
instructions.
DS026 (v3.0) November 12, 2001
Product Specification
www.xilinx.com
1-800-255-7778
5
XILINX [ XILINX, INC ]
