欢迎访问ic37.com |
会员登录 免费注册
发布采购

XC18V01VQ44C0799 参数 Datasheet PDF下载

XC18V01VQ44C0799图片预览
型号: XC18V01VQ44C0799
PDF下载: 下载PDF文件 查看货源
内容描述: [Configuration Memory, 128KX8, 15ns, Parallel/serial, CMOS, PQFP44, PLASTIC, VQFP-44]
分类和应用: 内存集成电路
文件页数/大小: 19 页 / 218 K
品牌: XILINX [ XILINX, INC ]
 浏览型号XC18V01VQ44C0799的Datasheet PDF文件第1页浏览型号XC18V01VQ44C0799的Datasheet PDF文件第2页浏览型号XC18V01VQ44C0799的Datasheet PDF文件第4页浏览型号XC18V01VQ44C0799的Datasheet PDF文件第5页浏览型号XC18V01VQ44C0799的Datasheet PDF文件第6页浏览型号XC18V01VQ44C0799的Datasheet PDF文件第7页浏览型号XC18V01VQ44C0799的Datasheet PDF文件第8页浏览型号XC18V01VQ44C0799的Datasheet PDF文件第9页  
R
XC18V00 Series of In-System Programmable Configuration PROMs
Table 1:
Pin Names and Descriptions (pins not listed are “no connect”)
(Continued)
Pin
Name
CF
Boundary
Scan
Order
22
21
20-pin
44-pin
Function
DATA OUT
OUTPUT
ENABLE
DATA OUT
OUTPUT
ENABLE
Pin Description
Allows JTAG CONFIG instruction to initiate FPGA
configuration without powering down FPGA. This is
an open-drain output that is pulsed Low by the
JTAG CONFIG command.
Chip Enable Output (CEO) is connected to the CE
input of the next PROM in the chain. This output is
Low when CE is Low and OE/RESET input is High,
AND the internal address counter has been
incremented beyond its Terminal Count (TC) value.
When OE/RESET goes Low, CEO stays High until
the PROM is brought out of reset by bringing
OE/RESET High.
GND is the ground connection.
VQFP
10
44-pin
PLCC
16
SOIC and
PLCC
7
(1)
CEO
11
12
21
27
13
GND
6, 18,
28 &
41
5
3, 12,
24 &
34
11
11
TMS
MODE
SELECT
The state of TMS on the rising edge of TCK
determines the state transitions at the Test Access
Port (TAP) controller. TMS has an internal 50K ohm
resistive pull-up on it to provide a logic “1” to the
device if the pin is not driven.
This pin is the JTAG test clock. It sequences the
TAP controller and all the JTAG test and
programming electronics.
This pin is the serial input to all JTAG instruction
and data registers. TDI has an internal 50K ohm
resistive pull-up on it to provide a logic “1” to the
system if the pin is not driven.
This pin is the serial output for all JTAG instruction
and data registers. TDO has an internal 50K ohm
resistive pull-up on it to provide a logic “1” to the
system if the pin is not driven.
Positive 3.3V supply voltage for internal logic and
input buffers.
Positive 3.3V or 2.5V supply voltage connected to
the output voltage drivers.
5
TCK
CLOCK
7
13
6
TDI
DATA IN
3
9
4
TDO
DATA OUT
31
37
17
V
CC
V
CCO
17, 35
& 38
8, 16,
26 &
36
23, 41
& 44
14, 22,
32 &
42
18 & 20
19
Notes:
1. Pin 7 is CF in Serial Mode, D4 in Slave-Parallel Mode for 20-pin packages.
DS026 (v3.0) November 12, 2001
Product Specification
1-800-255-7778
3