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XC18V01VQ44C0799 参数 Datasheet PDF下载

XC18V01VQ44C0799图片预览
型号: XC18V01VQ44C0799
PDF下载: 下载PDF文件 查看货源
内容描述: [Configuration Memory, 128KX8, 15ns, Parallel/serial, CMOS, PQFP44, PLASTIC, VQFP-44]
分类和应用: 内存集成电路
文件页数/大小: 19 页 / 218 K
品牌: XILINX [ XILINX, INC ]
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R
XC18V00 Series of In-System Programmable Configuration PROMs  
Table 1: Pin Names and Descriptions (pins not listed are no connect) (Continued)  
20-pin  
Boundary  
Scan  
Order  
44-pin 44-pin  
VQFP PLCC  
Pin  
Name  
SOICand  
PLCC  
Function  
Pin Description  
CF  
22  
21  
DATA OUT Allows JTAG CONFIG instruction to initiate FPGA  
configuration without powering down FPGA. This is  
10  
16  
7(1)  
OUTPUT  
an open-drain output that is pulsed Low by the  
ENABLE  
JTAG CONFIG command.  
CEO  
11  
12  
DATA OUT Chip Enable Output (CEO) is connected to the CE  
input of the next PROM in the chain. This output is  
21  
27  
13  
OUTPUT  
Low when CE is Low and OE/RESET input is High,  
ENABLE  
AND the internal address counter has been  
incremented beyond its Terminal Count (TC) value.  
When OE/RESET goes Low, CEO stays High until  
the PROM is brought out of reset by bringing  
OE/RESET High.  
GND  
TMS  
GND is the ground connection.  
6, 18,  
28 &  
41  
3, 12,  
24 &  
34  
11  
5
MODE  
SELECT  
The state of TMS on the rising edge of TCK  
determines the state transitions at the Test Access  
Port (TAP) controller. TMS has an internal 50K ohm  
resistive pull-up on it to provide a logic 1to the  
device if the pin is not driven.  
5
11  
TCK  
TDI  
CLOCK  
DATA IN  
This pin is the JTAG test clock. It sequences the  
TAP controller and all the JTAG test and  
programming electronics.  
7
3
13  
9
6
4
This pin is the serial input to all JTAG instruction  
and data registers. TDI has an internal 50K ohm  
resistive pull-up on it to provide a logic 1to the  
system if the pin is not driven.  
TDO  
DATA OUT This pin is the serial output for all JTAG instruction  
and data registers. TDO has an internal 50K ohm  
resistive pull-up on it to provide a logic 1to the  
system if the pin is not driven.  
31  
37  
17  
VCC  
Positive 3.3V supply voltage for internal logic and  
input buffers.  
17, 35 23, 41  
& 38 & 44  
18 & 20  
19  
VCCO  
Positive 3.3V or 2.5V supply voltage connected to  
the output voltage drivers.  
8, 16, 14, 22,  
26 &  
36  
32 &  
42  
Notes:  
1. Pin 7 is CF in Serial Mode, D4 in Slave-Parallel Mode for 20-pin packages.  
DS026 (v3.0) November 12, 2001  
www.xilinx.com  
3
Product Specification  
1-800-255-7778  
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