XC18V00 Series of In-System Programmable Configuration PROMs
R
Pinout and Pin Description
Table 1:
Pin Names and Descriptions (pins not listed are “no connect”)
Pin
Name
D0
Boundary
Scan
Order
4
3
D1
6
5
D2
2
1
D3
8
7
D4
24
23
D5
10
9
D6
17
16
D7
14
13
CLK
0
20-pin
44-pin
Function
DATA OUT
OUTPUT
ENABLE
DATA OUT
OUTPUT
ENABLE
DATA OUT
OUTPUT
ENABLE
DATA OUT
OUTPUT
ENABLE
DATA OUT
OUTPUT
ENABLE
DATA OUT
OUTPUT
ENABLE
DATA OUT
OUTPUT
ENABLE
DATA OUT
OUTPUT
ENABLE
DATA IN
Each rising edge on the CLK input increments the
internal address counter if both CE is Low and
OE/RESET is High.
When Low, this input holds the address counter
reset and the DATA output is in a high-impedance
state. This is a bidirectional open-drain pin that is
held Low while the PROM is reset. Polarity is NOT
programmable.
When CE is High, this pin puts the device into
standby mode and resets the address counter. The
DATA output pin is in a high-impedance state, and
the device is in low power standby mode.
43
5
3
19
25
12
14
20
9
25
31
14
9
15
7
(1)
27
33
15
Pin Description
D0 is the DATA output pin to provide data for
configuring an FPGA in serial mode.
VQFP
40
44-pin
PLCC
2
SOIC and
PLCC
1
D0-D7 are the output pins to provide parallel data
for configuring a Xilinx FPGA in
Slave-Parallel/SelectMap mode.
29
35
16
42
4
2
OE/
RESET
20
19
18
DATA IN
DATA OUT
OUTPUT
ENABLE
DATA IN
13
19
8
CE
15
15
21
10
2
1-800-255-7778
Product Specification
XILINX [ XILINX, INC ]
