R
XC18V00 Series of In-System Programmable Configuration PROMs
Pinout and Pin Description
Table 1: Pin Names and Descriptions (pins not listed are “no connect”)
Boundary
20-pin
44-pin 44-pin
VQFP PLCC
Pin
Scan
SOICand
PLCC
Name
Order
Function
Pin Description
D0
D1
D2
D3
D4
D5
D6
D7
CLK
4
3
DATA OUT D0 is the DATA output pin to provide data for
40
29
42
27
9
2
1
16
2
configuring an FPGA in serial mode.
OUTPUT
ENABLE
6
5
DATA OUT D0-D7 are the output pins to provide parallel data
for configuring a Xilinx FPGA in
35
4
OUTPUT
ENABLE
Slave-Parallel/SelectMap mode.
2
1
DATA OUT
OUTPUT
ENABLE
8
7
DATA OUT
33
15
31
20
25
15
7(1)
14
9
OUTPUT
ENABLE
24
23
DATA OUT
OUTPUT
ENABLE
10
9
DATA OUT
25
14
19
OUTPUT
ENABLE
17
16
DATA OUT
OUTPUT
ENABLE
14
13
DATA OUT
12
OUTPUT
ENABLE
0
DATA IN
Each rising edge on the CLK input increments the
internal address counter if both CE is Low and
OE/RESET is High.
43
13
5
3
8
OE/
RESET
20
19
18
DATA IN
When Low, this input holds the address counter
reset and the DATA output is in a high-impedance
state. This is a bidirectional open-drain pin that is
held Low while the PROM is reset. Polarity is NOT
programmable.
19
DATA OUT
OUTPUT
ENABLE
CE
15
DATA IN
When CE is High, this pin puts the device into
standby mode and resets the address counter. The
DATA output pin is in a high-impedance state, and
the device is in low power standby mode.
15
21
10
2
www.xilinx.com
DS026 (v3.0) November 12, 2001
1-800-255-7778
Product Specification
XILINX [ XILINX, INC ]
