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XC18V00 Series of In-System Programmable Configuration PROMs
The CF pin must be connected to the PROGRAM pin on the
FPGA(s) to use this feature.
Initiating FPGA Configuration
The XC18V00 devices incorporate a pin named CF that is
controllable through the JTAG CONFIG instruction. Execut-
ing the CONFIG instruction through JTAG pulses the CF low
for 300-500 ns, which resets the FPGA and initiates config-
uration.
The JTAG Programmer software can also issue a JTAG
CONFIG command to initiate FPGA configuration through
the “Load FPGA” setting.
Selecting Configuration Modes
The XC18V00 accommodates serial and parallel methods
of configuration. The configuration modes are selectable
through a user control register in the XC18V00 device. This
control register is accessible through JTAG, and is set using
the “Parallel mode” setting on the Xilinx JTAG Programmer
software. Serial output is the default programming mode.
Master Serial Mode Summary
The I/O and logic functions of the Configurable Logic Block
(CLB) and their associated interconnections are established
by a configuration program. The program is loaded either
automatically upon power up, or on command, depending
on the state of the three FPGA mode pins. In Master Serial
mode, the FPGA automatically loads the configuration pro-
gram from an external memory. Xilinx PROMs are designed
to accommodate the Master Serial mode.
ration, it must still be held at a defined level during normal
operation. The Xilinx FPGA families take care of this auto-
matically with an on-chip pull-up resistor.
Cascading Configuration PROMs
For multiple FPGAs configured as a serial daisy-chain, or a
single FPGA requiring larger configuration memories in a
serial or SelectMAP configuration mode, cascaded PROMs
provide additional memory (Figure 5). Multiple XC18V00
devices can be concatenated by using the CEO output to
drive the CE input of the downstream device. The clock
inputs and the data outputs of all XC18V00 devices in the
chain are interconnected. After the last bit from the first
PROM is read, the next clock signal to the PROM asserts its
CEO output Low and drives its DATA line to a high-imped-
ance state. The second PROM recognizes the Low level on
its CE input and enables its DATA output. See Figure 6.
Upon power-up or reconfiguration, an FPGA enters the Mas-
ter Serial mode whenever all three of the FPGA mode-select
pins are Low (M0=0, M1=0, M2=0). Data is read from the
PROM sequentially on a single data line. Synchronization is
provided by the rising edge of the temporary signal CCLK,
which is generated by the FPGA during configuration.
Master Serial Mode provides a simple configuration inter-
face. Only a serial data line, a clock line, and two control
lines are required to configure an FPGA. Data from the
PROM is read sequentially, accessed via the internal
address and bit counters which are incremented on every
valid rising edge of CCLK. If the user-programmable,
dual-function DIN pin on the FPGA is used only for configu-
After configuration is complete, address counters of all cas-
caded PROMs are reset if the PROM OE/RESET pin goes
Low.
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DS026 (v3.0) November 12, 2001
Product Specification
XILINX [ XILINX, INC ]
