R
XC18V00 Series of In-System Programmable Configuration PROMs
Vcc
Vcco
Vcc
Vcco
Vcc
4.7K
Vcc
DIN
MODE PINS*
DOUT
Vcc
DIN
MODE PINS*
Vcc
Vcco
D0
Vcc
Vcco
D0
Xilinx
FPGA
Vcc
Xilinx
FPGA
4.7K
XC18V00
Cascaded
PROM
1
2
3
4
TDI
TMS
TCK
CLK
CE
CEO
OE/RESET
CF
GND
TDO
GND
TDI
TMS
TCK
XC18V00
First
PROM
CLK
CE
CEO
OE/RESET
CF
TDO
Master
Serial
Slave
Serial
J1
TDI
TMS
TCK
TDO
**
CCLK
DONE
INIT
PROGRAM
TDI
TMS
TCK
TDO
CCLK
DONE
INIT
PROGRAM
TDI
TMS
TCK
TDO
* For Mode pin connections, refer to appropriate FPGA data sheet.
** Virtex, Virtex-E is 300 ohms, all others are 4.7K.
DS026_08_011501
Figure 5:
JTAG Chain for Configuring Devices in Master Serial Mode
DS026 (v3.0) November 12, 2001
Product Specification
1-800-255-7778
9