R
XC18V00 Series of In-System Programmable Configuration PROMs
Vcc
Vcco
Vcc
Vcco
Vcc
4.7K
Vcc
DIN
MODE PINS*
Vcc
DIN
MODE PINS*
DOUT
Xilinx
FPGA
Vcc
D0
Vcc
D0
Xilinx
FPGA
Vcco
Vcco
XC18V00
XC18V00
Vcc
4.7K
Master
Serial
Slave
Serial
Cascaded
PROM
First
PROM
**
J1
1
TDI
CLK
CE
TDI
CLK
CE
CCLK
DONE
CCLK
TDI
2
3
4
TMS
TMS
TMS
DONE
TCK
CEO
TCK
CEO
TCK
TDO
OE/RESET
CF
OE/RESET
CF
INIT
INIT
PROGRAM
PROGRAM
TDI
TDI
TDO
TDO
GND
GND
TMS
TCK
TMS
TCK
TDO
TDO
* For Mode pin connections, refer to appropriate FPGA data sheet.
** Virtex, Virtex-E is 300 ohms, all others are 4.7K.
DS026_08_011501
Figure 5: JTAG Chain for Configuring Devices in Master Serial Mode
DS026 (v3.0) November 12, 2001
www.xilinx.com
9
Product Specification
1-800-255-7778
XILINX [ XILINX, INC ]
