XC18V00 Series of In-System Programmable Configuration PROMs
Table 4:
Boundary Scan Instructions
Boundary-Scan
Command
BYPASS
SAMPLE/
PRELOAD
EXTEST
Binary
Code [7:0]
11111111
00000001
00000000
Description
Enables BYPASS
Enables boundary-scan
SAMPLE/PRELOAD operation
Enables boundary-scan
EXTEST operation
Enables boundary-scan
CLAMP operation
all outputs in high-impedance
state simultaneously
Enables shifting out
32-bit IDCODE
Enables shifting out
32-bit USERCODE
Initiates FPGA configuration
by pulsing CF pin Low
R
on the XC18V00 has two register stages that contribute to
the boundary-scan register, while each input pin only has
one register stage.
For each output pin, the register stage nearest to TDI con-
trols and observes the output state, and the second stage
closest to TDO controls and observes the High-Z enable
state of the pin.
For each input pin, the register stage controls and observes
the input state of the pin.
Identification Registers
The IDCODE is a fixed, vendor-assigned value that is used
to electrically identify the manufacturer and type of the
device being addressed. The IDCODE register is 32 bits
wide. The IDCODE register can be shifted out for examina-
tion by using the IDCODE instruction. The IDCODE is avail-
able to any other system component via JTAG.
The IDCODE register has the following binary format:
vvvv:ffff:ffff:aaaa:aaaa:cccc:cccc:ccc1
where
v = the die version number
f = the family code (50h for XC18V00 family)
a = the ISP PROM product ID (26h for the XC18V04)
c = the company code (49h for Xilinx)
Note: The LSB of the IDCODE register is always read as
logic “1” as defined by IEEE Std. 1149.1
lists the IDCODE register values for the XC18V00
devices.
Table 5:
IDCODES Assigned to XC18V00 Devices
ISP-PROM
XC18V01
XC18V02
XC18V04
XC18V256
->TD
O
Required Instructions
Optional Instructions
CLAMP
HIGHZ
IDCODE
USERCODE
11111010
11111100
11111110
11111101
XC18V00 Specific Instructions
CONFIG
11101110
Instruction Register
The Instruction Register (IR) for the XC18V00 is eight bits
wide and is connected between TDI and TDO during an
instruction scan sequence. In preparation for an instruction
scan sequence, the instruction register is parallel loaded
with a fixed instruction capture pattern. This pattern is
shifted out onto TDO (LSB first), while an instruction is
shifted into the instruction register from TDI. The detailed
composition of the instruction capture pattern is illustrated
in
Figure 3.
The ISP Status field, IR(4), contains logic “1” if the device is
currently in ISP mode; otherwise, it contains logic “0”. The
Security field, IR(3), contains logic “1” if the device has been
programmed with the security option turned on; otherwise, it
contains logic “0”.
IR[7:5]
TDI->
Notes:
000
IR[4]
ISP
Status
IR[3]
Security
IR[2]
0
IR[1:0]
01
IDCODE
05024093h
05025093h
05026093h
05022093h
05023093h
XC18V512
1. IR(1:0) = 01 is specified by IEEE Std. 1149.1
Figure 3:
Instruction Register Values Loaded into IR as
Part of an Instruction Scan Sequence
Boundary Scan Register
The boundary-scan register is used to control and observe
the state of the device pins during the EXTEST, SAM-
PLE/PRELOAD, and CLAMP instructions. Each output pin
The USERCODE instruction gives access to a 32-bit user
programmable scratch pad typically used to supply informa-
tion about the device’s programmed contents. By using the
USERCODE instruction, a user-programmable identifica-
tion code can be shifted out for examination. This code is
loaded into the USERCODE register during programming of
the XC18V00 device. If the device is blank or was not
loaded during programming, the USERCODE register con-
tains FFFFFFFFh.
6
1-800-255-7778
DS026 (v3.0) November 12, 2001
Product Specification
XILINX [ XILINX, INC ]
