0
R
XC18V00 Series of In-System
Programmable Configuration
PROMs
0
DS026 (v3.0) November 12, 2001
0
Product Specification
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Dual configuration modes
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-
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•
•
•
•
Serial Slow/Fast configuration (up to 33 MHz)
Parallel (up to 264 Mb/s at 33 MHz)
Features
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In-system programmable 3.3V PROMs for
configuration of Xilinx FPGAs
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Endurance of 20,000 program/erase cycles
Program/erase over full commercial/industrial
voltage and temperature range
5V tolerant I/O pins accept 5V, 3.3V and 2.5V signals
3.3V or 2.5V output capability
Available in PC20, SO20, PC44 and VQ44 packages
Design support using the Xilinx Alliance and
Foundation series software packages.
JTAG command initiation of standard FPGA
configuration
IEEE Std 1149.1 boundary-scan (JTAG) support
Simple interface to the FPGA
Cascadable for storing longer or multiple bitstreams
Low-power advanced CMOS FLASH process
Description
Xilinx introduces the XC18V00 series of in-system program-
mable configuration PROMs (Figure
Initial devices in this
3.3V family are a 4-megabit, a 2-megabit, a 1-megabit, a
512-Kbit, and a 256-Kbit PROM that provide an
easy-to-use, cost-effective method for re-programming and
storing large Xilinx FPGA or CPLD configuration bitstreams.
When the FPGA is in Master Serial mode, it generates a
configuration clock that drives the PROM. A short access
time after the rising CCLK, data is available on the PROM
DATA (D0) pin that is connected to the FPGA D
IN
pin. The
FPGA generates the appropriate number of clock pulses to
complete the configuration. When the FPGA is in Slave
Serial mode, the PROM and the FPGA are clocked by an
external clock.
CLK CE
When the FPGA is in Slave-Parallel or SelectMAP Mode, an
external oscillator generates the configuration clock that
drives the PROM and the FPGA. After the rising CCLK
edge, data are available on the PROMs DATA (D0-D7) pins.
The data is clocked into the FPGA on the following rising
edge of the CCLK. Neither Slave-Parallel nor SelectMAP
utilize a Length Count, so a free-running oscillator can be
used.
Multiple devices can be concatenated by using the CEO
output to drive the CE input of the following device. The
clock inputs and the DATA outputs of all PROMs in this
chain are interconnected. All devices are compatible and
can be cascaded with other members of the family or with
the XC17V00 one-time programmable Serial PROM family.
OE/Reset
TCK
TMS
TDI
TDO
Control
and
JTAG
Interface
Data
Memory
Address
Data
Serial
or
Parallel
Interface
7
CEO
D0 DATA
(Serial or Parallel
[Slave-Parallel/SelectMAP] Mode)
D[1:7]
Slave-Parallel and
SelectMAP Interface
CF
DS026_01_111201
Figure 1:
XC18V00 Series Block Diagram
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS026 (v3.0) November 12, 2001
Product Specification
1-800-255-7778
1
XILINX [ XILINX, INC ]
