R
XC18V00 Series of In-System Programmable Configuration PROMs
TAP Timing
XC18V00 TAP Characteristics
The XC18V00 family performs both in-system programming
and IEEE 1149.1 boundary-scan (JTAG) testing via a single
4-wire Test Access Port (TAP). This simplifies system
designs and allows standard Automatic Test Equipment to
perform both functions. The AC characteristics of the
XC18V00 TAP are described as follows.
Figure 4 shows the timing relationships of the TAP signals.
These TAP timing characteristics are identical for both
boundary-scan and ISP operations.
T
CKMIN
TCK
TMS
T
T
MSS
MSH
T
T
DIS
DIH
TDI
T
DOV
TDO
DS026_04_020300
Figure 4: Test Access Port Timing
TAP AC Parameters
Table 6 shows the timing parameters for the TAP waveforms shown in Figure 4
Table 6: Test Access Port Timing Parameters
Symbol
TCKMIN1
TCKMIN2
TMSS
Parameter
TCK minimum clock period
Min
100
50
10
25
10
25
-
Max
Units
-
-
ns
ns
ns
ns
ns
ns
ns
TCK minimum clock period, Bypass Mode
TMS setup time
-
TMSH
TMS hold time
-
TDIS
TDI setup time
-
TDIH
TDI hold time
-
TDOV
TDO valid delay
25
Connecting Configuration PROMs
Connecting the FPGA device with the configuration PROM
when a reconfiguration is initiated by a VCC glitch.
(see Figure 6).
•
•
The PROM CE input can be driven from the DONE pin.
The CE input of the first (or only) PROM can be driven
by the DONE output of the first FPGA device, provided
that DONE is not permanently grounded. CE can also
be permanently tied Low, but this keeps the DATA
output active and causes an unnecessary supply
current of 10 mA maximum.
•
The DATA output(s) of the PROM(s) drives the DIN
input of the lead FPGA device.
•
•
•
The Master FPGA CCLK output drives the CLK input(s)
of the PROM(s) (in Master Serial mode only).
The CEO output of a PROM drives the CE input of the
next PROM in a daisy chain (if any).
Slave-Parallel/SelectMap mode is similar to slave serial
mode. The DATA is clocked out of the PROM one byte
per CCLK instead of one bit per CCLK cycle. See FPGA
data sheets for special configuration requirements.
The OE/RESET input of all PROMs is best driven by
the INIT output of the lead FPGA device. This
connection assures that the PROM address counter is
reset before the start of any (re)configuration, even
DS026 (v3.0) November 12, 2001
www.xilinx.com
7
Product Specification
1-800-255-7778
XILINX [ XILINX, INC ]
