Philips Semiconductors
Preliminary specification
320 macrocell SRAM CPLD
PZ3320C/PZ3320N
also be disabled. Each macrocell can choose between an
XPLA2 Macrocell Architecture
asynchronous reset or an asynchronous preset function, but both
cannot be simultaneously used on the same register. The global rstn
function can always be used, regardless of whether or not
asynchronous reset or preset control terms are enabled. Control
terms CT2, CT3, CT4 and CT5 are used to enable or disable the
macrocell’s output buffer. Having four dedicated output enable
control terms ensures that the CoolRunner devices are PCI
compliant. The output buffers can also be always enabled or always
disabled. All CoolRunner devices also provide a Global 3-State
(gts) pin, which, when pulled high, will 3-State all the outputs of the
device. This pin is provided to support “In-Circuit Testing” or
“Bed-of-Nails” testing used during manufacturing.
Figure 4 shows the XPLA2 macrocell architecture used in the
PZ3320. The macrocell can be configured as either a D- or T-type
flip-flop or a combinatorial logic function. A D-type flip-flop is
generally more useful for implementing state machines and data
buffering while a T-type flip-flop is generally more useful in
implementing counters. Each of these flip-flops can be clocked from
any one of four sources. Two of the clock sources (CLK0 and CLK1)
are from the eight dedicated, low-skew, global clock networks
designed to preserve the integrity of the clock signal by reducing
skew between rising and falling edges. These clocks are designated
as a “synchronous” clocks and must be driven by an external
source. Both CLK0 and CLK1 can clock the macrocell flip-flops on
either the rising edge or the falling edge of the clock signal. The
other clock sources are designated as “asynchronous” and are
connected to two of the eight control terms (CT6 and CT7) provided
in each logic block. These clocks can be individually configured as
any PRODUCT term or SUM term equation created from the 36
signals available inside the logic block. Thus, in each Logic Block,
there are up to four possible clocks; and in each Fast Module, there
are up to 10 possible clocks. Throughout the entire device, there are
up to 40 possible clocks—eight from the dedicated, low-skew, global
clocks, and two for each of the 16 logic blocks.
For the macrocells in the Logic Block that are associated with I/O
pins, there are two feedback paths to the LZIA: one from the
macrocell, and one from the I/O pin. The LZIA feedback path before
the output buffer is the macrocell feedback path, while the LZIA
feedback path after the output buffer is the I/O pin feedback path.
When these macrocells are used as outputs, the output buffer is
enabled, and either feedback path can be used to feedback the logic
implemented in the macrocell. When the I/O pins are used as inputs,
the output buffer of these macrocells will be 3-Stated and the input
signal will be fed into the LZIA via the I/O feedback path. In this case
the logic functions implemented in the buried macrocell can be fed
back into the LZIA via the macrocell feedback path. For macrocells
that are not associated with I/O pins, there is one feedback path to
the LZIA. Logic functions implemented in these buried macrocells
are fed back into the LZIA via this path. All unused inputs and I/O
pins should be properly terminated. Please refer to the section on
terminations.
The remaining six control terms of each logic block (CT0–CT5) are
used to control the asynchronous preset/reset of the flip-flops and
the enable/disable of the output buffers in each macrocell. Control
terms CT0 and CT1 are used to control the asynchronous
preset/reset of the macrocell’s flip-flop. Note that the power-on reset
leaves all macrocells in the “zero” state when power is properly
applied, and that the preset/reset feature for each macrocell can
TO LZIA
D/T
Q
INIT
(P or R)
gts
CLK0
CLK0
GND
CT0
CT1
CT2
CT3
CT4
CT5
CLK1
CLK1
CT6
GND
CT7
V
CC
rstn
GND
SP00590
Figure 4. PZ3320 Macrocell Architecture
7
1998 Jul 22
XILINX [ XILINX, INC ]
