Philips Semiconductors
Preliminary specification
320 macrocell SRAM CPLD
PZ3320C/PZ3320N
Simple Timing Model
Figure 5 shows the PZ3320 timing model. The PZ3320 timing model
is very simple compared to the models of competing architectures.
There are three main timing parameters: the pin-to-pin delay for
combinatorial logic functions (t
PD
), the input pin to register set up
time (t
SU
), and the register clock to valid output time (t
CO
). As the
model shows, timing is only dependent on whether or not you use
the PLA array, and whether or not the logic function is created within
a single Fast Module or uses the GZIA. The timing starts with a set
time for t
PD
and t
SU
through the PAL array in a Fast Module, and
there are fixed delays added for use of the PLA array or the GZIA.
The t
CO
timing specification never changes. For example, a
combinatorial logic function of four or fewer product terms
constructed from inputs within the same logic block would have a
t
PD
delay of 7.5ns. If the logic function were more than four product
terms wide, the delay would be t
PD
plus the fixed PLA delay, or
7.5 + 1.5 = 9.0ns. A function that used the PAL array and inputs
from a different Fast Module would have a propagation delay of t
PD
plus the fixed GZIA delay, or 7.5 + 4.0 = 11.5ns.
This simple timing model allows designers to determine whether or
not the device will meet system timing specifications up front. In
competing devices, the user is unable to determine if the design will
meet system timing requirements until after the design has been fit
into the device. This is because the timing models of competing
architectures are very complex and include such things as timing
dependencies on the number of parallel expanders borrowed, the
fan-out of a signal, the varying number of X and Y routing channels
used, etc. The simplicity of the PZ3320 timing model gives you
pin-to-pin delay information before the design is set. Further, the
timing in the PZ3320 device will not vary with place and route
iterations caused by design changes. This allows the PZ3320 device
to meet your timing requirements even when you make changes to
the design.
Within a Fast Module:
INPUT PIN
t
PD_PAL
= COMBINATORIAL PAL
t
PD_PLA
= COMBINATORIAL PAL + PLA
OUTPUT PIN
INPUT PIN
REGISTERED
t
SU_PAL
= PAL
t
SU_PLA
= PAL + PLA
D
Q
REGISTERED
t
CO
OUTPUT PIN
GLOBAL CLOCK PIN
Using the Global ZIA:
INPUT PIN
t
PD_PAL
= COMBINATORIAL PAL + GZD
t
PD_PLA
= COMBINATORIAL PAL + PLA ,+ GZD
OUTPUT PIN
INPUT PIN
REGISTERED
t
SU_PAL
= PAL + GZD
t
SU_PLA
= PAL + PLA + GZD
D
Q
REGISTERED
t
CO
OUTPUT PIN
GLOBAL CLOCK PIN
SP00591B
Figure 5. PZ3320 Timing Model
1998 Jul 22
8
XILINX [ XILINX, INC ]
