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PZ3320N8YY 参数 Datasheet PDF下载

PZ3320N8YY图片预览
型号: PZ3320N8YY
PDF下载: 下载PDF文件 查看货源
内容描述: [LOADABLE PLD, 9.5ns, PBGA256, PLASTIC, BGA-256]
分类和应用: 时钟可编程逻辑
文件页数/大小: 32 页 / 488 K
品牌: XILINX [ XILINX, INC ]
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Philips Semiconductors  
Preliminary specification  
320 macrocell SRAM CPLD  
PZ3320C/PZ3320N  
(LZIA). The LZIA is a virtual crosspoint switch that connects the  
Logic Blocks to each other and to the GZIA. The feedback from all  
80 macrocells, input from the I/O pins, and the 64 bit input bus from  
the GZIA are input into the LZIA. The LZIA outputs 36 signals into  
each Logic Block and 64 signals into the GZIA.  
XPLA2 Fast Module  
Each Fast Module consists of four Logic Blocks of 20 macrocells  
each. Depending on the package, either 8 or 12 of the 20 macrocells  
in each Logic Block are connected to I/O pins, and the remaining  
macrocells are used as buried nodes. These four Logic Blocks are  
connected together by the Local Zero Power Interconnect Array  
MC0  
MC0  
MC1  
MC1  
36  
20  
36  
20  
LOGIC  
BLOCK  
LOGIC  
BLOCK  
I/O  
I/O  
MC19  
MC19  
LZIA  
MC0  
MC1  
MC0  
MC1  
36  
20  
36  
20  
LOGIC  
BLOCK  
LOGIC  
BLOCK  
I/O  
I/O  
MC19  
MC19  
64  
64  
SP00656  
Figure 2. Philips XPLA2 Fast Module  
5
1998 Jul 22  
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