Philips Semiconductors
Preliminary specification
320 macrocell SRAM CPLD
PZ3320C/PZ3320N
Software support for the PZ3320 is through industry standard CAE
tools (Cadence, Mentor, Synopsys, Synario, Viewlogic, MINC,
Exemplar Logic, and Orcad) as well as Philips’ own XPLA Designer.
Entry methods include both text (ABEL, PHDL, VHDL, Verilog)
and/or schematic. Design verification uses industry standard
simulators for functional and timing simulation, and development
tools are supported on personal computer, SPARC, and HP
Workstation platforms. Device fitting uses either MINC or Philips
Semiconductors developed tools.
ORDERING INFORMATION
PACKAGE,
ORDER CODE
DESCRIPTION
DRAWING NUMBER
PROPAGATION DELAY
PZ3320C7xx
PZ3320C7yy
PZ3320N8xx
PZ3320N8yy
160-pin LQFP, 7.5 ns t
Commercial temp. range, 3.3 volt power supply "10%
Commercial temp. range, 3.3 volt power supply "10%
Industrial temp. range, 3.3 volt power supply "10%
Industrial temp. range, 3.3 volt power supply "10%
PD
256-pin PBGA, 7.5 ns t
PD
160-pin LQFP, 7.5 ns t
PD
256-pin PBGA, 7.5 ns t
PD
3
1998 Jul 22
XILINX [ XILINX, INC ]
