R
Table 21: CLB Distributed RAM Switching Characteristics
-4
Symbol
Description
Min
Max
Units
Clock-to-Output Times
T
Time from the active edge at the CLK input to data appearing on the
distributed RAM output
SHCKO
-
2.35
ns
Setup Times
T
Setup time of data at the BX or BY input before the active transition at the
CLK input of the distributed RAM
DS
0.46
0.52
0.40
-
-
-
ns
ns
ns
T
Setup time of the F/G address inputs before the active transition at the CLK
input of the distributed RAM
AS
T
Setup time of the write enable input before the active transition at the CLK
input of the distributed RAM
WS
Hold Times
T
Hold time of the BX, BY data inputs after the active transition at the CLK
input of the distributed RAM
DH
0.15
0
-
-
ns
ns
T
T
Hold time of the F/G address inputs or the write enable input after the active
transition at the CLK input of the distributed RAM
AH, WH
Clock Pulse Width
, T Minimum High or Low pulse width at CLK input
T
1.01
-
ns
WPH WPL
Table 22: CLB Shift Register Switching Characteristics
-4
Symbol
Description
Min
Max
Units
Clock-to-Output Times
T
Time from the active edge at the CLK input to data appearing on the shift
register output
REG
-
4.16
ns
Setup Times
T
Setup time of data at the BX or BY input before the active transition at the
CLK input of the shift register
SRLDS
0.46
-
ns
Hold Times
T
Hold time of the BX or BY data input after the active transition at the CLK
input of the shift register
SRLDH
0.16
1.01
-
-
ns
ns
Clock Pulse Width
, T Minimum High or Low pulse width at CLK input
T
WPH WPL
DS635 (v2.0) September 9, 2009
www.xilinx.com
Product Specification
21
XILINX [ XILINX, INC ]
