R
Table 24: 18 x 18 Embedded Multiplier Timing (Continued)
-4 Speed Grade
Symbol
Description
Min
Max
Units
Clock Frequency
F
Internal operating frequency for a two-stage 18x18 multiplier using the
AREG and BREG input registers and the PREG output register
MULT
0
240
MHz
(1)
Notes:
1. Combinatorial delay is less and pipelined performance is higher when multiplying input data with less than 18 bits.
2. The PREG register is typically used in both single-stage and two-stage pipelined multiplier implementations.
3. Input registers AREG or BREG are typically used when inferring a two-stage multiplier.
Block RAM Timing
Table 25: Block RAM Timing
-4 Speed Grade
Symbol
Description
Min
Max
Units
Clock-to-Output Times
T
When reading from block RAM, the delay from the active transition
at the CLK input to data appearing at the DOUT output
BCKO
-
2.82
ns
Setup Times
T
T
T
T
Setup time for the ADDR inputs before the active transition at the
CLK input of the block RAM
BACK
BDCK
BECK
BWCK
0.38
0.23
0.77
1.26
-
-
-
-
ns
ns
ns
ns
Setup time for data at the DIN inputs before the active transition at
the CLK input of the block RAM
Setup time for the EN input before the active transition at the CLK
input of the block RAM
Setup time for the WE input before the active transition at the CLK
input of the block RAM
Hold Times
T
Hold time on the ADDR inputs after the active transition at the CLK
input
BCKA
0.14
0.13
-
-
ns
ns
T
Hold time on the DIN inputs after the active transition at the CLK
input
BCKD
T
T
Hold time on the EN input after the active transition at the CLK input
Hold time on the WE input after the active transition at the CLK input
0
0
-
-
ns
ns
BCKE
BCKW
DS635 (v2.0) September 9, 2009
www.xilinx.com
Product Specification
23
XILINX [ XILINX, INC ]
