R
Table 19: Test Methods for Timing Measurement at I/Os
Inputs and
Outputs
Inputs
Outputs
Signal Standard
(IOSTANDARD)
VREF (V)
VL (V)
VH (V)
RT (Ω)
VT (V)
VM (V)
Single-Ended
LVTTL
-
-
-
-
-
-
-
0
3.3
3.3
1M
1M
1M
1M
1M
1M
25
0
0
1.4
1.65
1.25
0.9
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
PCI33_3
0
0
2.5
0
0
1.8
0
0
0
1.5
0
0.75
0.6
1.2
0
Rising
Falling
Note 3
Note 3
0
0.94
2.03
VREF
VREF
VREF
VREF
25
3.3
0.9
1.8
0.9
1.25
HSTL_I_18
HSTL_III_18
SSTL18_I
SSTL2_I
0.9
1.1
V
REF – 0.5
VREF + 0.5
VREF + 0.5
VREF + 0.5
VREF + 0.75
50
VREF – 0.5
VREF – 0.5
VREF – 0.75
50
0.9
50
1.25
50
Differential
LVDS_25
-
-
-
-
-
-
-
-
-
VICM – 0.125
VICM – 0.125
VICM – 0.125
VICM – 0.3
VICM – 0.1
VREF – 0.5
VREF – 0.5
VREF – 0.5
VREF – 0.5
VICM + 0.125
VICM + 0.125
VICM + 0.125
VICM + 0.3
VICM + 0.1
VREF + 0.5
VREF + 0.5
VREF + 0.5
VREF + 0.5
50
1M
50
1M
50
50
50
50
50
1.2
0
VICM
VICM
VICM
VICM
VICM
VICM
VICM
VICM
VICM
BLVDS_25
MINI_LVDS_25
LVPECL_25
1.2
0
RSDS_25
1.2
0.9
1.8
0.9
1.25
DIFF_HSTL_I_18
DIFF_HSTL_III_18
DIFF_SSTL18_I
DIFF_SSTL2_I
Notes:
1. Descriptions of the relevant symbols are as follows:
V
V
V
– The reference voltage for setting the input switching threshold
– The common mode input voltage
– Voltage of measurement point on signal transition
REF
ICM
M
V – Low-level test voltage at Input pin
L
V
– High-level test voltage at Input pin
H
R – Effective termination resistance, which takes on a value of 1MΩ when no parallel termination is required
T
V – Termination voltage
T
2. The load capacitance (C ) at the Output pin is 0 pF for all signal standards.
L
3. According to the PCI specification.
DS635 (v2.0) September 9, 2009
www.xilinx.com
Product Specification
19
XILINX [ XILINX, INC ]
