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DS635 参数 Datasheet PDF下载

DS635图片预览
型号: DS635
PDF下载: 下载PDF文件 查看货源
内容描述: 了XA Spartan -3E汽车FPGA系列数据手册 [XA Spartan-3E Automotive FPGA Family Data Sheet]
分类和应用:
文件页数/大小: 37 页 / 723 K
品牌: XILINX [ XILINX, INC ]
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Table 16: Propagation Times for the IOB Input Path  
-4Speed  
Grade  
IFD_  
DELAY_  
VALUE  
Symbol  
Description  
Conditions  
Device  
Max  
Units  
Propagation Times  
(2)  
T
The time it takes for data to  
LVCMOS25  
,
0
All  
2.25  
ns  
IOPLI  
travel from the Input pin through IFD_DELAY_VALUE = 0  
the IFF latch to the I output with  
no input delay programmed  
(2)  
2
3
2
5
4
XA3S100E  
XA3S250E  
XA3S500E  
XA3S1200E  
XA3S1600E  
5.97  
6.33  
6.49  
8.15  
7.16  
ns  
ns  
ns  
ns  
ns  
T
The time it takes for data to  
LVCMOS25 ,  
IOPLID  
travel from the Input pin through IFD_DELAY_VALUE =  
the IFF latch to the I output with default software setting  
the input delay programmed  
Notes:  
1. The numbers in this table are tested using the methodology presented in Table 19 and are based on the operating conditions set forth in  
Table 6 and Table 9.  
2. This propagation time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. When this is  
true, add the appropriate Input adjustment from Table 17.  
Table 17: Input Timing Adjustments by IOSTANDARD  
Table 17: Input Timing Adjustments by IOSTANDARD  
Convert Input Time from  
LVCMOS25 to the Following  
Signal Standard  
Add the  
Adjustment Below  
Convert Input Time from  
LVCMOS25 to the Following  
Signal Standard  
Add the  
Adjustment Below  
(IOSTANDARD)  
-4 Speed Grade  
Units  
(IOSTANDARD)  
-4 Speed Grade  
Units  
Single-Ended Standards  
LVTTL  
Differential Standards  
LVDS_25  
0.43  
0.43  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
0.49  
0.39  
0.49  
0.27  
0.49  
0.49  
0.49  
0.30  
0.32  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
LVCMOS33  
LVCMOS25  
LVCMOS18  
LVCMOS15  
LVCMOS12  
PCI33_3  
BLVDS_25  
MINI_LVDS_25  
LVPECL_25  
0.98  
0.63  
0.27  
0.42  
0.12  
0.17  
0.30  
0.15  
RSDS_25  
DIFF_HSTL_I_18  
DIFF_HSTL_III_18  
DIFF_SSTL18_I  
DIFF_SSTL2_I  
HSTL_I_18  
HSTL_III_18  
SSTL18_I  
Notes:  
1. The numbers in this table are tested using the methodology  
presented in Table 19 and are based on the operating conditions  
set forth in Table 6, Table 9, and Table 11.  
SSTL2_I  
2. These adjustments are used to convert input path times originally  
specified for the LVCMOS25 standard to times that correspond to  
other signal standards.  
DS635 (v2.0) September 9, 2009  
www.xilinx.com  
Product Specification  
17  
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