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DS635 参数 Datasheet PDF下载

DS635图片预览
型号: DS635
PDF下载: 下载PDF文件 查看货源
内容描述: 了XA Spartan -3E汽车FPGA系列数据手册 [XA Spartan-3E Automotive FPGA Family Data Sheet]
分类和应用:
文件页数/大小: 37 页 / 723 K
品牌: XILINX [ XILINX, INC ]
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R
Clock Buffer/Multiplexer Switching Characteristics  
Table 23: Clock Distribution Switching Characteristics  
Maximum  
Description  
Symbol  
-4 Speed Grade  
Units  
Global clock buffer (BUFG, BUFGMUX, BUFGCE) I input to O-output  
delay  
T
1.46  
ns  
GIO  
Global clock multiplexer (BUFGMUX) select S-input setup to I0 and I1  
inputs. Same as BUFGCE enable CE-input  
T
0.63  
311  
ns  
GSI  
Frequency of signals distributed on global buffers (all sides)  
F
MHz  
BUFG  
18 x 18 Embedded Multiplier Timing  
Table 24: 18 x 18 Embedded Multiplier Timing  
-4 Speed Grade  
Symbol  
Description  
Min  
Max  
Units  
Combinatorial Delay  
T
Combinatorial multiplier propagation delay from the A and B inputs to  
the P outputs, assuming 18-bit inputs and a 36-bit product (AREG,  
BREG, and PREG registers unused)  
MULT  
(1)  
-
4.88  
ns  
Clock-to-Output Times  
T
Clock-to-output delay from the active transition of the CLK input to valid  
data appearing on the P outputs when using the PREG register  
MSCKP_P  
-
-
1.10  
ns  
ns  
(2)  
T
T
Clock-to-output delay from the active transition of the CLK input to valid  
data appearing on the P outputs when using either the AREG or BREG  
MSCKP_A  
MSCKP_B  
4.97  
(3)  
register  
Setup Times  
T
Data setup time at the A or B input before the active transition at the  
CLK when using only the PREG output register (AREG, BREG  
registers unused)  
MSDCK_P  
3.98  
-
ns  
(2)  
T
T
Data setup time at the A input before the active transition at the CLK  
when using the AREG input register  
MSDCK_A  
MSDCK_B  
0.23  
0.39  
-
-
ns  
ns  
(3)  
Data setup time at the B input before the active transition at the CLK  
(3)  
when using the BREG input register  
Hold Times  
T
Data hold time at the A or B input before the active transition at the CLK  
when using only the PREG output register (AREG, BREG registers  
unused)  
MSCKD_P  
-0.97  
(2)  
T
T
Data hold time at the A input before the active transition at the CLK  
when using the AREG input register  
MSCKD_A  
MSCKD_B  
0.04  
0.05  
(3)  
Data hold time at the B input before the active transition at the CLK  
(3)  
when using the BREG input register  
DS635 (v2.0) September 9, 2009  
www.xilinx.com  
Product Specification  
22  
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