R
Delay-Locked Loop
Table 26: Recommended Operating Conditions for the DLL
-4 Speed Grade
Symbol
Description
Min
Max
Units
Input Frequency Ranges
FCLKIN
CLKIN_FREQ_DLL
Frequency of the CLKIN clock input
5(2)
240(3)
MHz
Input Pulse Requirements
CLKIN_PULSE
CLKIN pulse width as a
percentage of the CLKIN
period
FCLKIN < 150 MHz
FCLKIN > 150 MHz
40%
45%
60%
55%
-
-
Input Clock Jitter Tolerance and Delay Path Variation(4)
CLKIN_CYC_JITT_DLL_LF
CLKIN_CYC_JITT_DLL_HF
CLKIN_PER_JITT_DLL
Cycle-to-cycle jitter at the
CLKIN input
FCLKIN < 150 MHz
FCLKIN > 150 MHz
-
-
-
-
300
150
1
ps
ps
ns
ns
Period jitter at the CLKIN input
CLKFB_DELAY_VAR_EXT
Allowable variation of off-chip feedback delay from the DCM output to
the CLKFB input
1
Notes:
1. DLL specifications apply when any of the DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, or CLKDV) are in use.
2. The DFS, when operating independently of the DLL, supports lower FCLKIN frequencies. See Table 28.
3. To support double the maximum effective FCLKIN limit, set the CLKIN_DIVIDE_BY_2 attribute to TRUE. This attribute divides the incoming
clock frequency by two as it enters the DCM. The CLK2X output reproduces the clock frequency provided on the CLKIN input.
4. CLKIN input jitter beyond these limits might cause the DCM to lose lock.
Table 27: Switching Characteristics for the DLL
-4 Speed Grade
Symbol
Description
Min
Max
Units
Output Frequency Ranges
CLKOUT_FREQ_CLK0
CLKOUT_FREQ_CLK90
CLKOUT_FREQ_2X
Frequency for the CLK0 and CLK180 outputs
Frequency for the CLK90 and CLK270 outputs
Frequency for the CLK2X and CLK2X180 outputs
Frequency for the CLKDV output
5
5
240
200
311
160
MHz
MHz
MHz
MHz
10
CLKOUT_FREQ_DV
0.3125
Output Clock Jitter(2,3,4)
CLKOUT_PER_JITT_0
CLKOUT_PER_JITT_90
CLKOUT_PER_JITT_180
CLKOUT_PER_JITT_270
CLKOUT_PER_JITT_2X
Period jitter at the CLK0 output
-
-
-
-
-
100
150
150
150
ps
ps
ps
ps
ps
Period jitter at the CLK90 output
Period jitter at the CLK180 output
Period jitter at the CLK270 output
Period jitter at the CLK2X and CLK2X180 outputs
[1% of
CLKIN period
+ 150]
CLKOUT_PER_JITT_DV1
CLKOUT_PER_JITT_DV2
Period jitter at the CLKDV output when performing integer
division
-
-
150
ps
ps
Period jitter at the CLKDV output when performing
non-integer division
[1% of
CLKIN period
+ 200]
DS635 (v2.0) September 9, 2009
www.xilinx.com
Product Specification
25
XILINX [ XILINX, INC ]
