R
Configurable Logic Block Timing
Table 20: CLB (SLICEM) Timing
-4 Speed Grade
Symbol
Description
Min
Max
Units
Clock-to-Output Times
T
When reading from the FFX (FFY) Flip-Flop, the time from the active
transition at the CLK input to data appearing at the XQ (YQ) output
CKO
-
0.60
ns
Setup Times
T
Time from the setup of data at the F or G input to the active transition
at the CLK input of the CLB
AS
0.52
1.81
-
-
ns
ns
T
Time from the setup of data at the BX or BY input to the active
transition at the CLK input of the CLB
DICK
Hold Times
T
Time from the active transition at the CLK input to the point where
data is last held at the F or G input
AH
0
0
-
-
ns
ns
T
Time from the active transition at the CLK input to the point where
data is last held at the BX or BY input
CKDI
Clock Timing
T
T
F
The High pulse width of the CLB’s CLK signal
The Low pulse width of the CLK signal
Toggle frequency (for export control)
0.80
0.80
0
-
-
ns
ns
CH
CL
572
MHz
TOG
Propagation Times
T
The time it takes for data to travel from the CLB’s F (G) input to the X
(Y) output
ILO
-
0.76
-
ns
ns
Set/Reset Pulse Width
T
The minimum allowable pulse width, High or Low, to the CLB’s SR
input
RPW_CLB
1.80
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 6.
DS635 (v2.0) September 9, 2009
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Product Specification
20
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