R
Table 15: Setup and Hold Times for the IOB Input Path
-4
Speed
Grade
IFD_
DELAY_
VALUE
Symbol
Description
Conditions
Device
Min
Units
Setup Times
TIOPICK
Time from the setup of data at the Input
LVCMOS25(2)
,
0
All
2.12
ns
pin to the active transition at the ICLK input IFD_DELAY_VALUE = 0
of the Input Flip-Flop (IFF). No Input Delay
is programmed.
TIOPICKD
Time from the setup of data at the Input
pin to the active transition at the IFF’s ICLK IFD_DELAY_VALUE =
input. The Input Delay is programmed. default software setting
LVCMOS25(2)
,
2
3
2
5
4
XA3S100E
XA3S250E
XA3S500E
XA3S1200E
XA3S1600E
6.49
6.85
7.01
8.67
7.69
ns
ns
ns
ns
ns
Hold Times
TIOICKP
Time from the active transition at the IFF’s LVCMOS25(2)
,
0
All
–0.76
ns
ICLK input to the point where data must be IFD_DELAY_VALUE = 0
held at the Input pin. No Input Delay is
programmed.
TIOICKPD
Time from the active transition at the IFF’s LVCMOS25(2)
ICLK input to the point where data must be IFD_DELAY_VALUE =
,
2
3
2
5
4
XA3S100E
XA3S250E
XA3S500E
XA3S1200E
XA3S1600E
–3.93
–3.51
–3.74
–4.30
–4.14
ns
ns
ns
ns
ns
held at the Input pin. The Input Delay is
programmed.
default software setting
Set/Reset Pulse Width
TRPW_IOB Minimum pulse width to SR control input
on IOB
All
1.80
ns
Notes:
1. The numbers in this table are tested using the methodology presented in Table 19 and are based on the operating conditions set forth in
Table 6 and Table 9.
2. This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, add the
appropriate Input adjustment from Table 17.
3. These hold times require adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, subtract
the appropriate Input adjustment from Table 17. When the hold time is negative, it is possible to change the data before the clock’s active
edge.
DS635 (v2.0) September 9, 2009
www.xilinx.com
Product Specification
16
XILINX [ XILINX, INC ]
