R
Platform Flash XL High-Density Configuration and Storage Device
Voltage Range
Table 28: Asynchronous Read AC Characteristics
Symbol
Alt
Parameter
Units
VDDQ
=
VDDQ =
3.0V to 3.6V
2.3V to 2.7V
TAVAV
TAVQV
TAVQV1
TRC
TACC
TPAGE
TOH
Address valid to next address valid
Min
85
85
30
0
85
85
30
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address valid to output valid (random) Max
Address valid to output valid (page)
Address transition to output transition
Chip enable Low to wait valid
Max
Min
(1)
TAXQX
TELTV
Max
Max
Min
17
85
0
17
85
0
(2)
TELQV
TCE
TLZ
Chip enable Low to output valid
Chip enable Low to output transition
Chip enable High to wait Hi-Z
(1)
TELQX
TEHTZ
Max
Min
17
0
17
0
(1)
TEHQX
TEHQZ
TGLQV
TGLQX
TOH
THZ
Chip enable High to output transition
Chip enable High to output Hi-Z
Output enable Low to output valid
Output enable Low to output transition
Output enable Low to wait valid
(1)
(2)
(1)
Max
Max
Min
17
25
0
17
25
0
TOE
TOLZ
TGLTV
Max
17
0
17
0
(1)
TGHQX
TOH
TDF
Output enable High to output transition Min
(1)
TGHQZ
Output enable High to output Hi-Z
Output enable High to wait Hi-Z
Address valid to latch enable High
Chip enable Low to latch enable High
Max
Max
Min
Min
17
17
10
10
9
17
17
10
10
9
TGHTZ
TAVLH
TELLH
TLHAX
TLLLH
TAVADVH
TELADVH
TADVHAX
Latch enable High to address transition Min
TADVLADVH Latch enable pulse width
Min
10
10
Latch enable Low to output valid
TLLQV
TADVLQV
(random)
Max
85
85
ns
Notes:
1. Sampled only, not 100% tested.
2. G may be delayed by up to T
– T
after the falling edge of E without increasing t
.
ELQV
GLQV
ELQV
DS617 (v3.0.1) January 07, 2010
www.xilinx.com
Product Specification
48
XILINX [ XILINX, INC ]
