R
Platform Flash XL High-Density Configuration and Storage Device
X-Ref Target - Figure 29
A22–A0
VALID ADDRESS
TAVKH
L
TLLKH
K(2)
TELKH
TKHQV
TELQV
E
TGLQV
TGLQX
G
TELQX
TGHTZ
High
W
Hi-Z
Hi-Z
DQ15–DQ0
VALID
TGLTV
TKHTV
READY_WAIT(1,2)
DS617_23_101608
Notes:
1. The READY_WAIT signal is configured to be active during wait state. READY_WAIT signal is active Low.
2. Address latched and data output on the rising clock edge. Either the rising or the falling edge of the clock signal, K, can be configured as the
active edge. Here, the active edge is the rising one.
3. The number of clock pulses in the dashed area depends on the latency (default latency = 7). The first clock that occurs while L is Low, latches
the address.
Figure 29: Single Synchronous Read AC Waveforms, CR4 = 0
DS617 (v3.0.1) January 07, 2010
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Product Specification
51
XILINX [ XILINX, INC ]
