R
Platform Flash XL High-Density Configuration and Storage Device
X-Ref Target - Figure 30
Hi-Z
VALID
VALID
VALID
VALID
DQ15–DQ0
A22–A0
VALID ADDRESS
TAVLH
TLLLH
L
TLLKH
TAVKH
TEHQX
TEHQZ
TKHQV
K(4)
E
Note 1
Note 3
TELKH
TKHAX
TEHEL
TGLQX
TGLQV
TGHQZ
TGHQX
G
TGLTV
TGHTZ
TEHTZ
TELTV
READY_WAIT(2,5)
Hi-Z
High
W
DS617_24_053008
Notes:
1. The number of clock cycles to be inserted depends on the X latency set in the Configuration Register.
2. The READY_ WAIT signal is configured to be active during wait state. READY_ WAIT signal is active Low.
3. The CLOCK signal can be held High or Low.
4. Address latched and data output on the rising clock edge. Either the rising or the falling edge of the clock signal, K, can be configured as the
active edge. Here, the active edge is the rising one.
5. From the moment data is valid, soon after G becomes asserted, the READY_WAIT signal reverts its previous level.
Figure 30: Synchronous Burst Read Suspend AC Waveforms, CR4 = 0
DS617 (v3.0.1) January 07, 2010
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Product Specification
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XILINX [ XILINX, INC ]
