R
Platform Flash XL High-Density Configuration and Storage Device
X-Ref Target - Figure 27
Hi-Z
DQ15–DQ0
A22–A0
VALID
VALID
VALID
NOT VALID
VALID
VALID ADDRESS
TAVLH
TLLLH
L
TEHQX
TEHQZ
TLLKH
TAVKH
TKHQV
TKHQX
K(4)
E
Note 1
TELKH
TKHAX
TEHEL
TGHQX
TGHQZ
TGLQX
G
TGLTV
High
Hi-Z
W
TELTV
TKHTV
TKHTX
Note 2
TEHTZ
Note 2
Note 2
READY_WAIT
Address
Latch
Boundary
Crossing
Valid
Data
X Latency
Valid Data Flow
Standby
DS617_22_053008
Notes:
1. The number of clock cycles to be inserted depends on the X latency set in the Burst Configuration Register.
2. The READY_WAIT signal can be configured to be active during wait state or one cycle before. READY_WAIT signal is active Low.
3. Address latched and data output on the rising clock edge.
4. Either the rising or the falling edge of the clock signal, K, can be configured as the active edge. Here, the active edge of K is the rising one.
5. The minimum system clock period is T
plus the FPGA data setup time.
KHQV
Figure 27: Synchronous Burst Read AC Waveforms, CR4 = 0
X-Ref Target - Figure 28
TKHKL
TKHKH
TF
TR
TKLKH
DS617_25_032708
Figure 28: Clock Input AC Waveform
DS617 (v3.0.1) January 07, 2010
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Product Specification
49
XILINX [ XILINX, INC ]
