R
Platform Flash XL High-Density Configuration and Storage Device
(1,2)
Table 29: Synchronous Read AC Characteristics
Voltage Range
Symbol
Alt
Parameter
Units
VDDQ
=
VDDQ =
3.0V to 3.6V
2.3V to 2.7V
TAVKH
TELKH
TAVCLKH Address Valid to Clock High
TELCLKH Chip Enable Low to Clock High
Chip Enable Low to Wait Valid
Min
Min
Max
9
9
9
9
ns
ns
ns
(3)
TELTV
17
17
Chip Enable pulse width
(subsequent synchronous reads)
TEHEL
Min
20
20
ns
(3)
TEHTZ
TKHAX
Chip Enable High to Wait Hi-Z
Max
Min
17
10
17
10
ns
ns
TCLKHAX Clock High to Address Transition
(4)
TKHQV
Clock High to Output Valid
TCLKHQV
Max
Min
16
2
16
2
ns
ns
(3)
TKHTV
TKHQX
Clock High to WAIT Valid
Clock High to Output Transition
TCLKHQX
(3)
TKHTX
TLLKH
Clock High to WAIT Transition
TADVLCLKH Latch Enable Low to Clock High
Min
Min
9
9
ns
ns
Clock Period (f = 54 MHz)(4)
Clock High to Clock Low
Clock Low to Clock High
19
19
(4)
TKHKH
TKHKL
TKLKH
TF
TCLK
Min
6
2
6
2
ns
Clock Fall or Rise Time
Max
ns
TR
Notes:
1. Sampled only, not 100% tested.
2. For other timings, refer to Table 28, page 50.
3. Parameter applies when READY_WAIT is configured (CR4) with the output WAIT function.
4. The minimum system clock period is T
+ FPGA data-to-CCLK setup time. See the FPGA data sheet for FPGA setup time.
KHQV
DS617 (v3.0.1) January 07, 2010
www.xilinx.com
Product Specification
50
XILINX [ XILINX, INC ]
