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Functional Description
Table 50: Serial Master Mode Connections
FPGA
Pin Name
Direction
Description
During Configuration
After Configuration
HSWAP
Input
User I/O Pull-Up Control. When Low during Drive at valid logic level
configuration, enables pull-up resistors in all throughout configuration.
I/O pins to respective I/O bank VCCO input.
User I/O
P
0: Pull-ups during configuration
1: No pull-ups
M[2:0]
Input
Mode Select. Selects the FPGA
configuration mode. See Design
Considerations for the HSWAP, M[2:0],
and VS[2:0] Pins.
M2 = 0, M1 = 0, M0 = 0.
Sampled when INIT_B goes
High.
User I/O
DIN
Input
Serial Data Input.
Receives serial data from
PROM’s D0 output.
User I/O
User I/O
CCLK
Output
Configuration Clock. Generated by FPGA
internal oscillator. Frequency controlled by
ConfigRate bitstream generator option. If
CCLK PCB trace is long or has multiple
connections, terminate this output to
maintain signal integrity. See CCLK Design
Considerations.
Drives PROM’s CLK clock input.
DOUT
INIT_B
Output
Serial Data Output.
Actively drives. Not used in
single-FPGA designs. In a
daisy-chain configuration, this pin
connects to DIN input of the next
FPGA in the chain.
User I/O
Open-drain Initialization Indicator. Active Low. Goes
bidirectional Low at start of configuration during
Connects to PROM’s OE/RESET
input. FPGA clears PROM’s
address counter at start of
configuration, enables outputs
during configuration. PROM also
holds FPGA in Initialization state
until PROM reaches Power-On
Reset (POR) state. If CRC error
detected during configuration,
FPGA drives INIT_B Low.
User I/O. If unused in
the application, drive
INIT_B High.
I/O
Initialization memory clearing process.
Released at end of memory clearing, when
mode select pins are sampled. Requires
external 4.7 kΩ pull-up resistor to VCCO_2.
DONE
Open-drain FPGA Configuration Done. Low during
bidirectional configuration. Goes High when FPGA
Connects to PROM’s chip-enable
(CE) input. Enables PROM
during configuration. Disables
PROM after configuration.
Pulled High via
external pull-up.
When High, indicates
that the FPGA
successfully
I/O
successfully completes configuration.
Requires external 330 Ω pull-up resistor to
2.5V.
configured.
PROG_B
Input
Program FPGA. Active Low. When asserted Must be High during
Low for 500 ns or longer, forces the FPGA to configuration to allow
Drive PROG_B Low
and release to
reprogram FPGA.
restart its configuration process by clearing
configuration memory and resetting the
DONE and INIT_B pins once PROG_B
returns High. Recommend external 4.7 kΩ
pull-up resistor to 2.5V. Internal pull-up value
may be weaker (see Table 78). If driving
externally with a 3.3V output, use an
open-drain or open-collector driver or use a
current limiting series resistor.
configuration to start. Connects
to PROM’s CF pin, allowing JTAG
PROM programming algorithm to
reprogram the FPGA.
DS312-2 (v3.8) August 26, 2009
www.xilinx.com
73
Product Specification
XILINX [ XILINX, INC ]
